Samsung Electronics Co., Ltd.

Snu Rdb Foundation

Young-chul Cho

Soo-Jung Ryu

Woong Seo

Moo-Kyoung Chung

Ho-Young Kim

Yoon-Jin Kim

Il-hyun Park

Tae-Wook Oh

Sung-Hoon Kim

Jin-Sae Jung

Yen-Jo Han

Jaejin Lee

Suk-jin Kim

Bernhard Egger

Joung-Yeal Kim

Seong-Hoon Jeong

Hee-jun Shim

Choon-Ki Jang

Do-Hyung Kim

Seong-Jin Jang

Kwang-il Park

Hyun-jung Kim

Si-hwa Lee

Tai-song Jin

Yong-sup Park

Dong-kwan Suh

Parichay Kapoor

Ji-hun Oh

Sung-Bae Park

Jeong-Wook Kim

Dong-Kwan Suh

Chul-soo Park

Seok-mo Chang

Kwang-hoon Son

A super-resolution processing method of a moving image is provided. The super-resolution processing method of a moving image includes sequentially inputting a plurality of input frames included in the video to any one of a recurrent neural network (RNN) for super-resolution processing and a convolutional neural network (CNN) for super-resolution processing, sequentially inputting a frame sequentially output from the any one of the RNN and the CNN to an additional one of the RNN and the CNN, and upscaling a resolution of the output frame by carrying out deconvolution with respect to a frame sequentially output from the additional one of the RNN and the CNN.

Super-resolution processing method for moving image and image processing apparatus therefor

A VLIW (Very Long Instruction Word) interface device includes a memory configured to store instructions and data, and a processor configured to process the instructions and the data, wherein the processor includes an instruction fetcher configured to output an instruction fetch request to load the instruction from the memory, a decoder configured to decode the instruction loaded on the instruction fetcher, an arithmetic logic unit (ALU) configured to perform an operation function if the decoded instruction is an operation instruction, a memory interface scheduler configured to schedule the instruction fetch request or a data fetch request that is input from the arithmetic logic unit, and a memory operator configured to perform a memory access operation in accordance with the scheduled instruction fetch request or data fetch request.

VLIW interface device and method for controlling the same

A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus.

Simulation device and distribution simulation system

An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

Apparatus and method for generating test cases for processor verification, and verification device

A latency management apparatus and method are provided. A latency management apparatus for a multiprocessor system having a plurality of processors and shared memory, when the shared memory and each of the processors is configured to generate a delayed signal, includes a delayed signal detector configured to detect the generated delayed signal; and one or more latency managers configured to manage an operation latency of any one of the processors upon detection of the delayed signal.

Latency management system and method for multiprocessor system

Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Apparatus and method for generating assertion based on user program code, and apparatus and method for verifying processor using assertion

A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.

Computing apparatus and method using X-Y stack memory

A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data.

Method of compressing and restoring configuration data

A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.

Apparatus to access multi-bank memory

A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation.

Verification supporting apparatus and verification supporting method of reconfigurable processor

Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost.

Apparatus and method for generating code overlay

Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.

Multi-port cache memory apparatus and method

A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address.

Multiprocessor using a shared virtual memory and method of generating a translation table

A simulation apparatus and method for a multicore system are provided. The simulation apparatus may prevent the occurrence of a data collision during the communication between modules and may reduce the overhead generated during simulation. The simulation apparatus may select a plurality of modules to be synchronized in terms of function execution timing based on timing information and may configure a multicore system architecture model using the selected modules. The simulation apparatus may acquire function execution timing information of the modules, control the execution of functions by the modules based on the acquired function execution timing information, and output the results of the control of the execution of functions by the modules.

Simulation apparatus and method for multicore system

A routing apparatus and a network apparatus that are capable of improving general system performance by compressing/decompressing data and transmitting the result of the compression/decompression, are provided. The routing apparatus may compress and/or decompress input data, and may transmit the compressed and/or decompressed input data.

Growing community of inventors

Yongin-si, South Korea

Young-chul Cho