Seoul National University

Advanced Micro Devices Corporation

Other

Samsung Electronics Co., Ltd.

Young-chang Joo

Taek Dong Chung

Jeong-Yun Sun

Hae-Ryung Lee

Seung-Min Lim

Seok Hee Han

Christy Mei-Chu Woo

Todd P Lukanc

Amit P Marathe

Deok-kee Kim

Sejun Kim

Jung-hun Sung

Kyoungdoug Min

Soo-jung Hwang

Ha-young You

Sung-yup Jung

Hyunjae Yoo

Kun-joong Park

Hong-seok Min

Seung-jin Song

A method for manufacturing a PDMS device in accordance with an exemplary embodiment of the present invention surface treats the entire surface of a pattern with a thiol group (—SH), so that a hydrogel may be connected to the surface of the pattern by a covalent bond under ultraviolet rays. Therefore, a PDMS device manufactured by the above method has an advantage in that the shape thereof may be stably maintained without the swelling or desorption of a hydrogel even when an electrolyte is filled in a pattern.

Method for manufacturing PDMS device and PDMS device manufactured thereby

Disclosed is an open-junction ionic transistor which includes: a substrate; a p type gel which is formed as a polyelectrolyte gel on the substrate; an n type gel which is formed as the polyelectrolyte gel on the substrate and having one side contacting one side of the p type gel; a first reservoir contacting the other side of the p type gel; a second reservoir contacting the other side of the n type gel; and an encapsulation layer covering the p type gel, the n type gel, the first reservoir, and the second reservoir, in which on the encapsulation layer, an injection unit for injecting an ion input is formed at a location corresponding to an interface contacting the p type gel and the n type gel and when reverse bias voltage is applied between the p type gel and the n type gel, the ion input injected through the injection unit is amplified and ionic current peak is generated.

Open-junction ionic transistor

A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.

Multi-bit memory device using multi-plug

A method of through-etching a substrate that is simplified and by which the flow of ions can be kept to be regular during a plasma dry etching process, is provided. According to this method, a buffer layer is formed on a first plane of the substrate, a metal layer is formed on the buffer layer, an etching mask pattern is formed on a second plane opposite to the first plane, and the substrate is through-etched with the etching mask pattern as an etching mask. Preferably, the substrate is formed of a single-crystal silicon, the buffer layer is formed of silicon dioxide, and the metal layer is formed of aluminum.

Method of through-etching substrate

A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing CV or IV measurements between the copper lines and the silicon wafer.

Barrier layer integrity test

The concentration of metal atoms in a field area between two trench structures is determined by applying a voltage on one of the trench structures and grounding the other. The resultant current flow between the trench structures is measured and used as an indicator of metal concentration in the field area.

Method for determining metal concentration in a field area

Growing community of inventors

Seoul, South Korea

Young-chang Joo