Hynix Semiconductor Inc.

Skhynix Inc.

Hyundai Electronics Industries Co. Ltd.

Young-Bo Shim

Jae-Boum Park

Woo-Soon Kang

Yung-Jin Gang

A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

Semiconductor device and operating method thereof

A semiconductor memory device includes a fuse array circuit including a row fuse region and a column fuse region, and suitable for outputting fuse information from row fuse sets and from column fuse sets and outputting programmed row and column addresses as row and column fall data, during a boot-up operation; a fuse array control circuit suitable for storing a fail address based on a fail cell information during a repair operation, searching unused fuse sets from the row fuse region and the column fuse region based on the fuse information during the boot-up operation, and controlling the fail address to be programmed in the unused fuse sets during a rupture operation; and a row and column redundancy circuit suitable for performing a row or column redundancy operation in correspondence to the row and column fail data.

Semiconductor memory device for performing a post package repair operation and operating method thereof

A semiconductor device includes a nonvolatile memory block suitable for outputting data stored in a plurality of nonvolatile memory cells included therein based on first control information, and programming data in the nonvolatile memory cells based on second control information; a control block suitable for generating the first control information based on an initialization signal, wherein the control block sequentially generates the second control information and the first control information when a program mode is activated; and a test control block suitable for deactivating the nonvolatile memory block and determining whether at least one control signal among a plurality of control signals included in the first and second control information is normally generated, in a test operation on the program mode.

Semiconductor device, semiconductor memory device and memory system

A semiconductor memory device includes a bit line sense amplifier block array, upper and lower memory cell arrays and a sense amplifier controller. The bit line sense amplifier block array senses and amplifies data of a memory cell array. The upper and the lower memory cell arrays are respectively connected to upper and lower sides of the bit line sense amplifier block array and store the data in the memory cell array. The sense amplifier controller selectively connects one of the upper and lower memory cell arrays to the bit line sense amplifier block array in response to an active command, and releases the connection when a corresponding one of the upper and lower memory cell arrays are not selected but overdriven.

Method of driving a semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array

A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode selection signal enabled in an external address refresh mode, an address selector for outputting the refresh address from the refresh counter as a selection row address in a normal refresh mode and outputting the internal address from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal, and a row address decoder for generating a row address selection signal for sequentially accessing word lines by decoding the selection row address.

Refresh control circuit and method for semiconductor memory device

A refresh control circuit for a semiconductor memory device includes a refresh controller configured to control the number of times a refresh signal is enabled during one refresh period in response to a refresh mode entering signal which indicates the start of a refresh mode, and a mode determination signal having refresh mode information, a refresh counter configured to output a row address for a refresh operation by counting the refresh signal in response to an active signal enabled in an active mode, and a row address decoder configured to decode the row address to generate a row address selection signal for sequentially accessing word lines within a cell array.

Semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array

A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

Counter circuit and method of operating the same

A semiconductor memory device is provided. The semiconductor memory device includes: an oscillation means for generating a self-refresh enable signal and a self-refresh period pulse having a predetermined period in response to a self-refresh signal; a shift register for generating a self-refresh period level signal maintaining a different level at every self-refresh period defined by the self-refresh enable signal and the self-refresh period pulse, in response to a test mode signal; a multiplexing means for selectively outputting a data signal and the self-refresh period level signal in response to the test mode signal; and an output buffer for buffering the output signal of the multiplexing means to output the buffered signal.

Semiconductor memory device

A data output control apparatus and method of a semiconductor memory device exactly synchronize the first read data with a clock signal by solving a problem that the first read data is faster than the clock signal as much as a transit time from a voltage level Vddq/2 to a power voltage Vddq or a ground voltage Vssq. For the purpose, the apparatus for sequentially outputting a plurality of read data stored in the semiconductor memory device includes a first path through which a first read data output control signal for controlling the output of the first read data among the plurality of read data is passing, and a second path through which a second data output control signal for controlling the output of the other read data following the first read data among the plurality of read data is passing, wherein the first read data output control signal is delayed as much as the transit time and outputted through the first path in response to a preamble time control signal for reporting the start of a data read operation.

Apparatus and method for controlling data output of a semiconductor memory device

A pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and complementary global I/O lines to store the data, includes: a data detecting unit, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating unit for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage units for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting unit.

Semiconductor memory device having pipe register operating at high speed

A synchronous semiconductor memory device having a plurality of external signal input buffer and a plurality of latch circuits, includes: a clock buffer for receiving an external clock signal to generate a buffered clock signal; a chip select buffer for receiving an external chip select signal and the buffered clock signal from said clock buffer to generate a buffered chip select signal, an inverted buffered chip select signal and a latch control signal, wherein the latch control signal is activated when the external clock signal is at the rising edge and the external chip select signal is low; a plurality of external signal buffers for receiving external signals to generate buffered signals and inverted buffered signals; and a plurality of latch circuits for latching and outputting the buffered signals and the inverted buffer signals to an internal logic circuit in response to the latch control signal.

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Gyeonggi-do, South Korea

Young-Bo Shim