Samsung Electronics Co., Ltd.

Young-Bae Yoon

Ki-Hyun Kim

Jeong-Dong Choe

Dong-Hoon Jang

Sung-Hun Lee

Joongshik Shin

Hyunmog Park

Seokjung Yun

Da Woon Jeong

Kwang-Ho Kim

Hyun-Mog Park

Jong-Hyuk Kim

Joong-Shik Shin

Choong-Ho Lee

Tae-Yong Kim

Soyeon Kim

Hee-Soo Kang

Keon-Soo Kim

Dongseog Eun

Seong-Soon Cho

Kwang-Shik Shin

Se-Hoon Lee

Jung-Hwan Park

Keonsoo Kim

Yoonmoon Park

Min-Tai Yu

Hyun-Chul Back

Jibong Park

Hanyoung Lee

Youngseop Rah

Woo-Jung Kim

A three-dimensional semiconductor memory device includes a substrate, an electrode structure including electrodes vertically stacked on the substrate and each having a pad portion, electrode separation structures penetrating the electrode structure and apart from each other in a second direction, and contact plugs coupled to the pad portions. The contact plugs comprise first contact plugs and second contact plugs apart in the second direction from the first contact plugs. The electrode separation structures comprise a first electrode separation between the first and second contact plugs. The first contact plugs are apart in the second direction at a first distance from the first electrode separation structure. The second contact plugs are apart in the second direction from the first electrode separation structure at a second distance, different from the first distance.

Three dimensional semiconductor memory devices

Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same

A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Vertical memory devices and methods of manufacturing the same

In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

Method of forming a pattern structure for a semiconductor device

A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

Method of manufacturing a semiconductor device

Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

Non-volatile memory devices including shared bit lines and methods of fabricating the same

A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

Semiconductor device including driving transistors

Semiconductor device

Growing community of inventors

Hwaseong-si, South Korea

Young-Bae Yoon