Magnachip Semiconductor, Inc.

Key Foundry Co., Ltd

Young Bae Kim

Kwang Il Kim

Francois Hebert

Jin Yeong Son

Jae Hyung Jang

Jun Hyun Kim

Jin Woo Moon

In Sik Jung

Kyung Ho Lee

In Taek Oh

Jung Hwan Lee

Su Jin Kim

In Chul Jung

Myeong Seok Kim

I-Shan Sun

Young Ju Kim

Seung Guk Kim

Provided are a semiconductor device, a method of manufacturing the same, and a method of forming a uniform doping concentration of each semiconductor device when manufacturing a plurality of semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable by using ion blocking patterns to provide a semiconductor device with uniform doping concentration and a higher breakdown voltage obtainable as a result of such doping.

Semiconductor and method of fabricating the same

A semiconductor device includes a source region and a drain region formed in a substrate and having different conductivity types, an insulating film formed between the source region and the drain region, a deep well region formed under the insulating film, and a pinch-off region formed under the insulating film and having a same conductivity type as the deep well region, wherein a depth of a bottom surface of the pinch-off region is different from a depth of a bottom surface of the deep well region.

High voltage semiconductor device having bootstrap diode

A single poly multi time program (MTP) cell includes a second conductivity-type well, a sensing transistor comprising a drain, a sensing gate, and a source, a drain electrode connected to the drain, a source electrode connected to the source; a control gate connected to the sensing gate of the sensing transistor, and a control gate electrode, wherein the sensing transistor, the drain electrode, the source electrode, the control gate, and the control gate electrode are located on the second conductivity-type well.

Single poly multi time program cell and method of operating the same

Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.

Semiconductor device with high voltage field effect transistor and junction field effect transistor

A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.

Integrated semiconductor device and method for manufacturing the same

A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.

High voltage semiconductor device

Provided is a semiconductor and method of manufacturing the same, and a method of forming even doping concentration of respective semiconductor device when manufacturing multiple semiconductor devices. When a concentration balance is disrupted due to an increase in doping region size, doping concentration is still controllable in example by using ion injected blocking pattern. Thus, the examples relate to a semiconductor and manufacture device with even doping, and high breakdown voltage obtainable as a result of such doping.

An example provides a semiconductor device including an insulator with a predetermined thickness between a well region of a semiconductor substrate and a resistor of polysilicon. The insulator has a structure that is able to withstand an ultrahigh voltage, and thereby allows the manufacture of a semiconductor device resistor that can bear an ultrahigh voltage without increasing the size of a semiconductor substrate and a semiconductor device including such a resistor. Other examples provide a method for manufacturing such a semiconductor device.

Ultrahigh voltage resistor, semiconductor device, and the manufacturing method thereof

The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.

Semiconductor structure having a junction field effect transistor and a high voltage transistor and method for manufacturing the same

Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer.

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Cheongju-si, South Korea

Young Bae Kim