Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Postech Academy-industry Foundation

Gwangju Institute of Science and Technology

Doosan Corporation

Young-Bae Kim

Chang-jung Kim

Seung-ryul Lee

Man Chang

Dong-Soo Lee

Chang-bum Lee

Myoung-jae Lee

Kyung-min Kim

Ji-hyun Hur

Hyeok-Sang Oh

Sang-Hoon Ahn

Woo-Jin Lee

Sung-Ho Kim

Heung-Kyu Kwon

Woo-Jong Cho

Seong-jun Park

Yun-Hee Lee

Mun-cheol Choi

Young-soo Park

Sang-Woo Lee

Myeong-Suk Kim

Tae-Hyung Kim

Hwan-Hee Cho

Kyung-Min Kim

Jong-Hwan Lee

Chang-Woong Chu

In-kyeong Yoo

Hee-Seok Lee

In-gyu Baek

Kyoung-woo Lee

Sung-Wook Kim

Seung-eon Ahn

Yong-Hoon Kim

In-Kyeong Yoo

Hoon-Seok Seo

Sung-Jin Kang

Eun-ju Cho

Su-Hyun Bark

Se-hyun Park

Ja-Yong Koo

Yun-ho Lee

Sae-jin Kim

Masayuki Terai

Chul-Woo Kim

Jong-Seong Kim

Jeong-Hoon Ahn

Jong-Sam Kim

Youn-Seon Kang

Hyun-Sang Hwang

Bo-soo Kang

Hong-sun Hwang

Eui-Bok Lee

Hyun-sang Hwang

Ho-Cheol Park

Ki-hwan Kim

Lijie Zhang

Jun-Jung Kim

Hyo-Seon Lee

Chang-Jun Lee

Bok-Sik Myung

Jin-Hyeung Park

Ji-Hyun Hur

Chang-Bum Lee

Suk-Hee Jang

Hoe-Moon Kim

Kyung-Tae Na

Seong-Jun Park

Chang-Jung Kim

Seung-Ryul Lee

Myoung-Jae Lee

Mun-Cheol Choi

Yun-Ho Lee

An integrated circuit device includes a metal film and a complex capping layer covering a top surface of the metal film. The metal film includes a first metal, and penetrates at least a portion of an insulating film formed over a substrate. The complex capping layer includes a conductive alloy capping layer covering the top surface of the metal film, and an insulating capping layer covering a top surface of the conductive alloy capping layer and a top surface of the insulating film. The conductive alloy capping layer includes a semiconductor element and a second metal different from the first metal. The insulating capping layer includes a third metal.

Integrated circuit device and method of manufacturing the same

An integrated circuit (IC) device includes a lower wiring structure including a lower metal film. The lower wiring structure penetrates at least a portion of a first insulating film disposed over a substrate. The IC device further includes a capping layer covering a top surface of the lower metal film, a second insulating film covering the capping layer, an upper wiring structure penetrating the second insulating film and the capping layer, and electrically connected to the lower metal film, and an air gap disposed between the lower metal film and the second insulating film. The air gap has a width defined by a distance between the capping layer and the upper wiring structure.

An organic light-emitting device includes: a first electrode; a second electrode opposite the first electrode; an emission layer between the first electrode and the second electrode; a hole transport region between the first electrode and the emission layer; and an electron transport region between the emission layer and the second electrode, the electron transport region including an electron control layer, wherein the hole transport region includes at least one compound selected from a first compound represented by Formula 1 and a second compound represented by Formula 2, and the electron control layer includes a third compound represented by Formula 3: 

Organic light-emitting device

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Wiring structures and semiconductor devices

A glass film laminate includes a carrier glass including a rough surface, a smooth surface surrounding the rough surface, the rough surface having a relatively large surface roughness and the smooth surface having a relatively small surface roughness, and a passage rough surface connected to the rough surface; and a glass film laminated on the rough surface and the smooth surface of the carrier glass.

Glass film laminate, method of manufacturing the same, and method of manufacturing glass film

In one embodiment, the memory element may include a first electrode, a second electrode spaced apart from the first electrode, a memory layer between the first electrode and the second electrode, and an auxiliary layer between the memory layer and the second electrode. The auxiliary layer provides a multi-bit memory characteristic to the memory layer.

Multi-bit memory elements, memory devices including the same, and methods of manufacturing the same

A memory device may include a first electrode and a second electrode spaced apart from the first electrode. The memory device may further include a memory element disposed between the first electrode and the second electrode and a switching element disposed between the first electrode and the second electrode. The switching element may be configured to control signal access to the memory element. The memory device may further include a barrier layer disposed between the memory element and the switching element, the barrier layer including an insulation material.

Memory device and apparatus including the same

Provided is a semiconductor package including a package substrate having lands, a first semiconductor device mounted on the package substrate and having a bottom surface on which first lines are disposed, and solder balls respectively electrically connected to the lands of the package substrate with the first lines of the first semiconductor device. The first semiconductor device includes a first substrate, and through-substrate via (TSV) plugs that vertically pass through the first substrate. The TSV plugs are respectively vertically aligned with the first lines, overlap first regions corresponding to 70% or less of diameters of the solder balls from central axes of the solder balls, and do not overlap second regions corresponding to the remaining 30% or more of diameters of the solder balls from the central axes of the solder balls. Adjacent ones of the TSV plugs are arranged at irregular intervals with respect to each other.

Semiconductor devices having through-substrate via plugs and semiconductor packages including the same

A three-terminal synapse device may include a drain layer formed on a substrate, a gate layer formed on the drain layer, a source layer vertically stacked on the substrate and facing the drain layer and the gate layer. First and second vertical insulating layers may be formed between the source layer and a stack including the drain layer and the gate layer. The first and second vertical insulating layers have different ion mobilities from each other. The first and second vertical insulating layers may cover side surfaces of the drain layer and the gate layer. The ion mobility of the second vertical insulating layer may be greater than that of the first vertical insulating layer.

Three-terminal synapse device and method of operating the same

A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.

Semiconductor memory device having three-dimensional cross point array

A resistive switching device includes a first material layer between a first electrode and a second electrode. The first material layer has a first region and a second region parallel to the first region. The first region corresponds to a conducting path formed in the first material layer, and is configured to switch from a low-resistance state to a high-resistance state in response to an applied voltage that is greater than or equal to a first voltage. The second region is configured to switch to a first resistance value that is less than a resistance value of the first region in the high-resistance state when the applied voltage is greater than or equal to a second voltage. The first region remains constant or substantially constant when the second region has the first resistance value.

Resistive switching devices and memory devices including the same

An apparatus for processing an image, including: a body; a lens module disposed on the body; and a control ring disposed on the lens module, wherein the control ring is configured to change a setting value of a setting item.

Apparatus for processing an image having detachable lens and a ring for setting photographing parameter values

Bipolar memory cells and a memory device including the same are provided, the bipolar memory cells include two bipolar memory layers having opposite programming directions. The two bipolar memory layers may be connected to each other via an intermediate electrode interposed therebetween. The two bipolar memory layers may have the same structure or opposite structures.

Bipolar memory cells and memory devices including the same

Growing community of inventors

Seoul, South Korea

Young-Bae Kim