Cirrus Logic Inc.

Silicon Laboratories Inc.

Legerity, Inc.

Cirrus Logic International Semiconductor Limited

Younes Djadi

Nariankadu Datatreya Hemkumar

Sachin Deo

Scott Thomas Haban

Russell Croman

Nathan Daniel Pozniak Buchanan

Eric B Smith

Javier Elenes

Christopher Jackson

Daniel T Bogard

Michael R May

Yan Zhou

Junsong Li

George Tyson Tuttle

Vijayakumaran Velayudhan Nair

Wai-Shun Shum

Russell Alvin Schultz

Carroll S Vance

Akhilesh Persha

Lokesh Duraiappah

James P McFarland

Roshan Kamath

Wei Han

Franz Weller

Nathan Buchanan

Nariankadu D Hemkumar

A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.

System with dynamically selectable firmware image sequencing for production test, debug, prototyping

A distributed processing system with multiple systems connected by an inter-system communication interface. Each system has a memory programmed with multiple firmware images each having a distinct entry point, a processor, a writable (by another system of the distributed processing system) hardware register initially seeded with an initial firmware image entry point, and a controller external to the processor that, prior to an initial reset, reads the entry point from the hardware register and causes the processor to begin fetching instructions at the initial entry point. Prior to a subsequent reset of the processor, the external controller facilitates a transition to another firmware image by reading its entry point from the hardware register and causing the processor to begin fetching instructions at the other entry point. Each system may have multiple processors and multiple associated hardware registers writeable by another processor of the system or a by host processor.

Multi-processor system with dynamically selectable multi-stage firmware image sequencing and distributed processing system thereof

A system includes primary and secondary devices (e.g., camera controllers that drive voice coil motors) each having respective outputs and a communication link. The primary device includes first and second hardware timers, each of which expires at a time derived from a periodic control loop trigger. At first timer expiration, the primary transmits first updated values to the secondary. At second timer expiration, primary device hardware picks up and applies second updated values to the primary device outputs. In response to receiving the first updated values from the primary device, the secondary device applies the received first updated values to its outputs. The primary/secondary device combination provide a sufficient number of total outputs that they could not individually provide and further synchronize the outputs with small skew through the timers, which are programmable to also accommodate processing of inputs (e.g., from voice coil motor sensors) to compute the outputs.

System and method for providing increased number of time synchronized outputs by using communicating primary and secondary devices

A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and based on position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the at least one secondary camera controller device. The primary and secondary camera controller devices receive respective primary and secondary sensor data from the position sensors, send the respective primary and secondary sensor data to the other camera controller device via the communication link, process the primary and secondary sensor data and the position information to generate respective primary and secondary control data, and drive the respective primary and secondary control data to the actuators concurrently.

Multi-chip camera controller system with inter-chip communication

A system for using actuators to control an image sensor and/or lens based on sensor data received from position sensors and position information for the image sensor and/or lens received from a host processor includes a primary camera controller device, at least one secondary camera controller device, and at least one communication link connecting the primary camera controller device and the secondary camera controller device. The primary camera controller device processes the received sensor data and the received position information to generate control data, sends a secondary portion of the control data to the secondary camera controller device via the communication link, and drives a primary portion of the control data to the actuators. The secondary camera controller device drives the received secondary portion of the control data to the actuators concurrently with the primary camera controller device driving the primary portion of the control data to the actuators.

A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.

Systems and methods for context-dependent multicore interrupt facilitation

A system may include a processing engine and an analog-to-digital conversion interface subsystem communicatively coupled to the processing engine. The processing engine may be configured to process feedback data converted from analog feedback data to digital feedback data, wherein the feedback data includes a plurality of data stream sequences converted from the analog feedback data to the digital feedback data at a sample rate and based on processing of the feedback data, generate digital control signals for controlling a system under control. The analog-to-digital conversion interface subsystem may be configured to flexibly control the processing of the processing engine and the generation of digital control signals by the processing engine to minimize latency in the generation of the digital control signals due to processing of the processing engine.

Flexible latency-minimized delivery and management of disparate-rate data streams and sub-streams for processing

A system may include a switchable power domain configured to selectively be powered on and powered off during operation of the system and an always-on power domain configured to remain powered on during operation of the system, the always-on power domain including a power management unit. The power management unit may be configured to, in response to a shut down condition for powering down the switchable power domain, determine a state of a bus transaction on a communication bus between the switchable power domain and the always-on power domain and control one or more control signals for controlling the communication bus in order to manipulate completion of the bus transaction to prevent at least one of corruption of data of the bus transaction and a system freeze associated with the bus transaction.

Protecting against memory corruption and system freeze during power state transitions in a multi-power domain system

A system for reading a plurality of subset views of an evolving data store may include for each subset view, a plurality of memory buffers comprising at least three buffers. The system may also include control circuitry for controlling the plurality of memory buffers of the plurality of subset views, the control circuitry configured to maintain, for each subset view, a variable defining a most-recently updated buffer of the plurality of buffers such that a read request for such subset view will respond with data of the most-recently updated buffer of such subset view; and responsive to an update of data of the evolving data store: (i) determine, for each subset view, a selected data buffer of the plurality of buffers other than the most-recently updated buffer for such subset view to write updated subset view information; (ii) cause, for each subset view, the updated subset view information for such subset view to be written to the selected data buffer for such subset view; and (iii) substantially simultaneously across all of the plurality of subset views, update the variables defining the most-recently updated buffer of the plurality of subset views such that a subsequent read request for a subset view will respond with the updated subset view information for such subset view.

Discrete exchange and update of multiple consistent subset views of an evolving data store

Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate.

Circuit devices and methods for re-clocking an input signal

Systems and methods are disclosed that implement multiple inter-chip (IC) links to communicate digital signals and data between multiple tuner circuit chips of a radio frequency (RF) antenna diversity system. The multiple IC communication links may be employed, for example, to simultaneously communicate different signals and/or data between individual tuner circuit chips of a multi-signal type antenna diversity system in an asynchronous manner, and may be employed to achieve simultaneous antenna diversity for multiple RF signal types using a scalable IC communication link architecture that includes multiple IC communication links to interconnect a varying number of RF tuner circuit chips.

Systems and methods using multiple inter-chip (IC) links for antenna diversity and/or debug

An integrated circuit includes a first port for conducting a first plurality of signals, a second port for conducting a second plurality of signals, a data path coupled between the first port and the second port, a controller, and a processor having an input and an output. In a first mode, the controller causes the data path to conduct at least one signal received on the first port to the second port. In a second mode, the controller controls the processor to output signals to the second port.

Integrated circuit with inter-chip link for boot-up

A tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor synchronizes the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset. The digital signal processor performs a selected antenna diversity operation on the first and second DSP frames to produce an output signal.

Antenna diversity system with frame synchronization

In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.

Antenna diversity system with multiple tuner circuits having multiple operating modes and methods

A line card for interfacing with a plurality of subscriber lines includes a plurality of data processors and a tone detector. Each of the data processors is associated with one of the subscriber lines. The tone detector is adapted to detect one of a plurality of activation tones on a selected subscriber line. The plurality of activation tones include a first activation tone having an active portion and a silent portion. The active and silent portions repeat periodically at a first frequency having a first period. A second activation tone has a phase reversal portion repeating at a second frequency and having a second period. The tone detector is further adapted to sequence between the subscriber lines at a predetermined interval. The predetermined interval is based on the first and second periods. The tone detector is adapted to signal the data processor associated with the selected subscriber line in response to detecting one of the activation tones.

Growing community of inventors

Austin, TX, United States of America

Younes Djadi