Skhynix Inc.

Youncheul Kim

Hyunsu Yoon

Jeongsu Jeong

Yonggu Kang

Jeongtae Hwang

Sungho Kim

Sungju Son

Dongue Ko

Igsoo Kwon

Yeonuk Kim

Kwidong Kim

HyunJu Yoon

Kwanweon Kim

Bokmoon Kang

Gwangyoung Stanley Jeong

Gwangyeong Stanley Jeong

A memory device includes a boot-up control unit configured to control a start of boot-up operation by starting the boot-up operation when an initialization signal is activated, and ignore the initialization signal after a complete signal is activated, a nonvolatile memory unit configured to store repair data, and output the stored repair data during the boot-up operation, a plurality of registers configured to store the repair data outputted from the nonvolatile memory unit, a plurality of memory banks configured to replace a normal cell with a redundant cell, using the repair data stored in the corresponding registers among the plurality of resistors, and a verification unit configured to generate the complete signal to notify that the boot-up operation is completed.

Integrated circuit and memory device

An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

E-fuse array circuit

A memory device includes a non-volatile memory configured to store a repair data and output the repair data in response to an initialization signal, a plurality of registers configured to store the repair data outputted from the non-volatile memory, a plurality of memory banks configured to replace normal cells with redundant cells by using the repair data stored in corresponding registers among the plurality of registers, a verification circuit configured to generate a completion signal for informing that transfer of the repair data from the non-volatile memory to the plurality of registers is completed, and an output circuit configured to output the completion signal to a device other than the memory device.

Memory device, memory system including a non-volatile memory configured to output a repair data in response to an initialization signal

An e-fuse array circuit includes a program gate line and a word line gate line that are stretched in parallel to each other, and a metal line formed over the program gate line and the word line gate line to cover the program gate line and the word line gate line, the metal line connected to the program gate line through a plurality of contact plugs disposed at a given distance.

A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability.

One-time program cell array circuit and memory device including the same

An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated.

A method for testing a memory device includes entering a test mode in which multiple memory banks operate in a same manner, allowing a row corresponding to a row address in the multiple memory banks to be activated, latching a bank address and the row address corresponding to the multiple memory banks, writing same data in a column selected by a column address in the multiple memory banks, reading the data written in the writing of the data from the multiple memory banks, checking whether the data read from the multiple memory banks in the reading of the data are equal to each other, and programming the bank address and the row address to a nonvolatile memory when the data read from the multiple memory banks are different from each other.

Memory device and test method thereof

An integrated circuit includes a high voltage generator generating a high voltage, a negative voltage generator generating a negative voltage, a divided voltage generator generating a divided voltage by dividing the power source voltage and supplying it to a read voltage terminal, a first power gate supplying the high voltage or the divided voltage to a program voltage terminal, a second power gate supplying the negative voltage or the ground voltage to a deactivation voltage terminal, a third power gate supplying the ground voltage or the divided voltage to an activation voltage terminal, and an e-fuse array circuit operating using voltage of the program voltage terminal as a program voltage, voltage of the divided voltage terminal as a read voltage, voltage of the activation voltage terminal as an activation voltage, and voltage of the deactivation voltage terminal as a deactivation voltage.

Integrated circuit including e-fuse array circuit

A method for programming a resistive memory device includes: programming a resistive memory; generating a verification data based on comparison result of a voltage, which is generated from a current flowing through the resistive memory, and a verification reference voltage which is higher than a read reference voltage used for a normal read operation; and deciding whether to end a program operation based on the verification data.

Resistive memory device and programming method thereof

A resistive memory device includes a first cell array configured to store data, a second cell array configured to share column lines of the first cell array, a first error correction cell array configured to store an error correction code that corresponds to the data to be stored in the first cell array, and a second error correction cell array configured to share column lines of the first error correction cell array.

Growing community of inventors

San Jose, CA, United States of America

Youncheul Kim