Neuchips Corporation

Tsinghua University

Youn-Long Lin

Chao-Yang Kao

Ping Chao

Huang-Chih Kuo

Jian-Wen Chen

Chiung-Liang Lin

Hui-Ting Yang

Chih-wei Chang

Shi-Hao Chen

Tao-Yi Lee

YuShan Ruan

A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.

Harmonic densely connecting method of block of convolutional neural network model and system thereof, and non-transitory tangible computer readable recording medium

A matrix multiplier and an operation method thereof are provided. The matrix multiplier includes a plurality of first input lines, a plurality of second input lines and a computing array. The computing array includes a plurality of multiplication accumulation (MAC) cells. A first MAC cell of the plurality of MAC cells is coupled to a first corresponding input line of the plurality of first input lines and a second corresponding input line of the plurality of second input lines to receive a first input value and a second input value to perform a multiplication accumulation operation. When at least one of the first input value and the second input value is a specified value, the multiplication accumulation operation of the first MAC cell is disabled.

Matrix multiplier and operation method thereof

A feature map caching method of a convolutional neural network includes a connection analyzing step and a plurality of layer operation steps. The connection analyzing step is for analyzing a network to establish a convolutional neural network connection list. The convolutional neural network connection list includes a plurality of tensors and a plurality of layer operation coefficients. Each of the layer operation coefficients includes a step index, at least one input operand label and an output operand label. The step index as a processing order for the layer operation step. At least one of the layer operation steps is for flushing at least one of the tensors in a cache according to a distance between the at least one of the layer operation steps and a future layer operation step of the layer operation steps. The distance is calculated according to the convolutional neural network connection list.

Feature map caching method of convolutional neural network and system thereof

A computing system and a compressing method for neural network parameters are provided. In the method, multiple neural network parameters are obtained. The neural network parameters are used for a neural network algorithm. Every at least two neural network parameters are grouped into an encoding combination. The number of neural network parameters in each encoding combination is the same. The encoding combinations are compressed with the same compression target bit number. Each encoding combination is compressed independently. The compression target bit number is not larger than a bit number of each encoding combination. Thereby, the storage space can be saved and excessive power consumption for accessing the parameters can be prevented.

Computing system and compressing method for neural network parameters

A computing device and an operation method thereof are provided. The computing device includes multiple memories and an indexer circuit. The indexer circuit is separately coupled to the memories through multiple memory channels. The indexer circuit determines an arrangement of at least one lookup table to at least one of the memories according to a characteristic of the at least one lookup table and a transmission bandwidth of the memory channels, so as to balance a transmission load of the memory channels.

Computing device and operation method thereof

A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a number of a plurality of input channels of a plurality of input feature maps, an input feature map tile size, a number of a plurality of output channels of a plurality of output feature maps and an output feature map tile size for a convolutional layer operation. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation. The convolution calculating step is for performing the convolutional layer operation with the input feature maps to produce the output feature maps according to a memory-adaptive processing technique, and the memory-adaptive processing technique includes a dividing step and an output-group-first processing step.

Memory-adaptive processing method for convolutional neural network

A matrix multiplication device and an operation method thereof are provided. The matrix multiplication device includes calculation circuits, a control circuit, a multiplication circuit, and a routing circuit. The calculation circuits produce multiply-accumulate values. The control circuit receives a plurality of first element values of a first matrix. The control circuit classifies the first element values into at least one classification value. The multiplication circuit multiplies the classification value by a second element value of a second matrix in a low power mode to obtain at least one product value. The routing circuit transmits each of the product values to at least one corresponding calculation circuit in the calculation circuits in the low power mode.

Matrix multiplication device and operation method thereof

A computing device and an operation method thereof are provided. The computing device includes a plurality of memories and a processing circuit. The processing circuit is coupled to the memories. The processing circuit dynamically determines which of the plurality of memories to store at least one lookup table according to characteristics of the at least one lookup table. The processing circuit may then execute at least one algorithm by using the at least one lookup table.

A curve function device and an operation method thereof are provided. The curve function device includes a lookup table, a weight calculation circuit, and a linear function circuit. According to first partial bits of an input value, a bias value of a current segment and a bias value of a next segment can be extracted from the lookup table. The weight calculation circuit can calculate a weight value of the current segment according to the bias value of the current segment and the bias value of the next segment. The linear function circuit can calculate a linear function value by using the bias value of the current segment, the weight value of the current segment, and second partial bits of the input value. This linear function value can be used as an approximate value of the curve function.

Curve function device and operation method thereof

A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a plurality of input channels of an input feature map tile and a plurality of output channels of an output feature map tile for a convolutional layer operation of the convolutional neural network. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation among a total input size, a total output size and the cache free space size of the feature map cache. The convolution calculating step is for performing the convolutional layer operation according to a memory-adaptive processing technique.

Memory-adaptive processing method for convolutional neural network and system thereof

A fast vector multiplication and accumulation circuit is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector. A scheduler is configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively. A self-accumulating adder is signally connected to the scheduler and includes a compressor, at least two delay elements and at least one shifter. The compressor is configured to add the scheduled operands to generate a plurality of compressed operands. The at least two delay elements are connected to the compressor. The shifter is configured to shift one of the compressed operands. An adder is signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.

Fast vector multiplication and accumulation circuit

An apparatus of automatic vehicle suspension system is provided. Road conditions are precisely monitored for reducing vibrations of cabin. Uneven road surface is crossed over through fast expansion and compression of shock absorber just in time. The present invention uses real-time control of an active suspension system to build road contour at real time. At the same time, control signals having better suspension dynamic characteristics are updated at real time for further obtaining a superior and precise suspension system.

Apparatus of automatic vehicle suspension system using real-time road contour

The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state.

Power booting sequence control system and control method thereof

A compression method and a compression system for display frames of QFHD (quad full high definition) resolution are provided and applied to the image encoding/decoding environment of the H.264/AVC image encoding standard of the QFHD resolution and the effective dictionary base compression and de-compression algorithm, the image data compression rate can be tremendously raised at the resolution of 1080 HD (High Definition) content and the average memory data rate is greatly decreased. Hence only a bus with a lower frequency as 57 MHz can be done for the real-time of the resolution of 1080 HD content.

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Hsinchu, Taiwan

Youn-Long Lin