Sunrise Memory Corporation

Skhynix Inc.

Youn Cheul Kim

Eli Harari

Robert D Norman

Khandker N Quader

Richard S Chernicoff

Tianhong Yan

Sayeef Salahuddin

Frank Sai-Keung Lee

Mehrdad Mofidi

A first circuit formed on a first semiconductor substrate is wafer-bonded to a second circuit formed on a second memory circuit, wherein the first circuit includes quasi-volatile or non-volatile memory circuits and wherein the second memory circuit includes fast memory circuits that have lower read latencies than the quasi-volatile or non-volatile memory circuits, as well as logic circuits. The volatile and non-volatile memory circuits may include static random-access memory (SRAM) circuits, dynamic random-access memory (DRAM) circuits, embedded DRAM (eDRAM) circuits, magnetic random-access memory (MRAM) circuits, embedded MRAM (eMRAM), or any suitable combination of these circuits.

High capacity memory circuit with low effective latency

A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

Quasi-volatile system-level memory

Semiconductor systems are provided. The semiconductor system includes a boot-up operation circuit and a timing sensor. The boot-up operation circuit transmits control data stored in a fuse array portion to a first data latch unit and a second data latch unit. The timing sensor detects timings of internal control signals to generate a restart signal. The boot-up operation circuit re-transmits the control data to the first and second data latch units.

Semiconductor devices including E-fuse arrays

A circuit includes a first buffer configured to provide data on a signal line. The first buffer may be powered by a first power supply voltage. The circuit further includes a tri-state buffer coupled to receive the data provided on the signal line. The tri-state buffer may be powered by a second power supply voltage that has a magnitude greater than that of the first power supply voltage. During operation, the tri-state buffer may be activated for a predetermined period of time during which data is made available on the signal line.

Circuit for small swing data line and method of operating the same

A circuit includes a plurality of buffers configured to provide data on a corresponding signal line. Each of the plurality of buffers may be coupled to a power supply voltage through a corresponding diode. A plurality of receiving circuits may be coupled to receive the data provided on a corresponding one of the plurality of signal lines. The plurality of receiving circuits may be directly powered by the power supply voltage.

Growing community of inventors

Saratoga, CA, United States of America

Youn Cheul Kim