Changxin Memory Technologies, Inc.

Youming Liu

Deyuan Xiao

Guangsu Shao

Yunsong Qiu

Xingsong Su

Yi Jiang

Weiping Bai

Yuhan Zhu

The present disclosure provides a transistor and a manufacturing method thereof, and a memory, relates to the technical field of semiconductors. The transistor includes: a channel, wherein an accommodation space is formed therein; a gate, provided with a first end and a second end that are opposite, wherein the first end of the gate is located inside the accommodation space, and the second end of the gate is located outside the accommodation space; a dielectric layer, located between the gate and a channel, insulating and isolating the gate and the channel; a source, provided at one end of the channel; and a drain, provided at the other end of the channel, wherein the drain and the source are arranged at intervals along a length direction of the channel, and the source, the drain, and the channel are each made of a semiconductor material.

Transistor and manufacturing method thereof, and memory

Embodiments relates to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where an isolation trench is formed in the substrate; forming a first isolation layer in the isolation trench, where the first isolation layer fills the isolation trench, and a crack extending to an upper surface of the first isolation layer along a vertical direction is formed in the first isolation layer; removing part of the first isolation layer by etching back to form an isolation filling groove in communication with a top opening of the crack; and forming a second isolation layer in the isolation filling groove to plug the top opening of the crack, where the first isolation layer and the second isolation layer jointly constitute an isolation structure.

Semiconductor structure and method for fabricating same

The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a forming method thereof. The forming method of a semiconductor device includes: providing a substrate; etching the substrate to form first recesses and second recesses located below the first recesses and communicating with the first recesses; forming a bit line in the second recesses; forming, at bottoms of the first recesses, an isolation layer covering the bit line; enlarging an inner diameter of the first recess above the isolation layer; and forming a gate layer on a sidewall of the first recess whose inner diameter is enlarged.

Semiconductor device having bottom bit line and narrow channel, and forming method thereof

Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.

Three-dimensional semiconductor structure and formation method thereof

A method for forming a semiconductor structure includes the following operations. A substrate is provided. The substrate includes double heterostructures arrayed along a first direction and a second direction. Each of the double heterostructures includes a first semiconductor layer, a second semiconductor layer and another first semiconductor layer sequentially arranged along the first direction. A forbidden band gap of the first semiconductor layer is different from a forbidden band gap of the second semiconductor layer. The first direction is perpendicular to the second direction, and both the first direction and the second direction are parallel to a direction of a plane where the substrate is located. A double gate structure is formed on sidewalls of each of the double heterostructures along the first direction.

Semiconductor structure and method for forming same

Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.

2T0C semiconductor structure

A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.

Semiconductor structure, method for manufacturing same

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a memory cell array, located on the substrate, the memory cell array includes a plurality of transistor units, each of the transistor units includes a first transistor and a second transistor extending along a first direction and electrically connected to each other, and the first direction is parallel to the substrate; a first bit line, penetrating the memory cell array and electrically connected to the first transistor; a second bit line, penetrating the memory cell array and electrically connected to the second transistor; a first word line, electrically connected to the first transistor; and a second word line, electrically connected to the second transistor.

Semiconductor structure and manufacturing method thereof

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a semiconductor substrate, the semiconductor substrate is provided with first trenches extending along a first direction and second trenches extending along a second direction, the first trenches intersect with the second trenches to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench is filled with a first dielectric layer, a second dielectric layer is provided on a top of the semiconductor pillar, and a third dielectric layer is provided on a sidewall of the first trench; an isolation layer, located in the semiconductor substrate below the first trenches and extending along the second direction; and a bit line, located on a surface of the isolation layer and extending along the second direction, the bit line is connected to a bottom of the semiconductor pillar.

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

Growing community of inventors

Hefei, China

Youming Liu