Hynix Semiconductor Inc.

Youk Hee Kim

Bok Rim Ko

Sun Mo An

Young Joo Kim

A precharge signal generator having a latch signal generator, an internal signal generator, and a pulse generator is presented. The latch signal generator is configured to generate a latch signal that is activated in response to an auto-precharge command and inactivated in response to an active pulse. The internal signal generator is configured to generate an internal signal activated when a delayed active signal and the latch signal are all activated. The pulse generator is configured to generate a precharge signal including a pulse that is activated in a period for which the internal signal is being active.

Precharge signal generator and semiconductor memory device

A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.

Pipe latch circuit and semiconductor memory device using the same

A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.

Driving strength control circuit and data output circuit in semiconductor device

Disclosed are a thermal code transmission circuit and a semiconductor memory device using the same. The thermal code transmission circuit includes a select signal generator which generates a select signal in response to a first enable signal, a level signal generator which receives the first enable signal to generate a level signal, an update signal generator which receives the level signal and a first update signal to generate a second update signal, a latch unit which receives a thermal code in response to the second update signal and outputs the thermal code as an output thermal code, and a thermal code output unit which selectively outputs the output thermal code in response to the select signal.

Thermal code transmission circuit and semiconductor memory device using the same

A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives the decoding signal and outputs a trimming signal adjusted by a low level test signal.

Growing community of inventors

Seoul, South Korea

Youk Hee Kim