Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Fujitsu Corporation

Mitsubishi Denki Kabushiki Kaisha

Nihon Musen Kabushiki Kaisha

Zaidanhouzin Kasenzyouho-Senta

Youichi Suzuki

Makoto Segawa

Sumako Shiraishi

Fujio Masuoka

Shigeo Ohshima

Shigeru Suzuki

Shoji Ariizumi

Takeo Kondo

Masayuki Doi

Shigeyuki Shimauchi

Takenori Nakamura

Toshiaki Ohno

Yoshiyuki Kanbayashi

Yasuo Misawa

Tadahiko Nakao

Tetsuro Sato

Susumu Miyamoto

Yasuo Koiwai

Touru Uruno

A semiconductor memory device having a normal mode of reading and writing data from and to a selected memory cell of a memory cell array. The semiconductor memory device is characterized by control means for switching the normal operation mode to a test mode in response to a test mode signal applied to a certain input terminal, selecting all desired memory cells of the memory cell array at a time, and allowing data applied to a data input terminal to be written to all the selected and desired memory cells at one time.

Detector circuit for testing semiconductor memory device

The memory device of this invention includes a plurality of memory cell blocks each having a plurality of memory cells disposed in a matrix form. A memory cell selector selects a predetermined number of the memory cells in each memory cell block in accordance with external address signals. A sense amplifier unit amplifies data read from the selected memory cells for data read. A data output unit outputs the data amplified by the sense amplifier unit. A block selector selects a desired one or more of the memory cell blocks as data write blocks for data write. A data write unit writes data in the selected memory cells in the selected blocks. A sense amplifier controller supplies, during the data write, a signal to the sense amplifier unit to make the sense amplifier unit inactive, and during the data read supplies a signal to the sense amplifier unit to make the sense amplifier unit active.

Memory cell array divided type semiconductor memory device

One cell of the first cell group CG and one cell of the second cell group CxG are selected simultaneously in response to address signals A1 and A2; data of these selected cells are amplified by the first and second sense amplifiers SA1 and SA2, respectively as sense outputs dA, dA, dB, dB; these sense outputs are given to a select circuit SEL including output buffer circuits OB; the select circuit outputs any of the first and second sense outputs to an output circuit Q17, Q18 in response to select signals ODA, ODB applied from an output switch circuit OSW on the basis of a specific address signal A12, A12. Since plural sense outputs based upon plural cell data are previously outputted simultaneously from the sense amplifiers to the select circuit and then one of the sense outputs is selected on the basis of a specific address, the cell data can be read at high speed as compared with when data are simply read from cells without simultaneous data transfer and data selection.

Semiconductor memory device having improved access to addresses

In the semiconductor memory device, memory cells are divided into plural blocks; each block is further divided into plural I/O unit groups; and furthermore each I/O unit group is divided into plural small groups. The word lines provided for each small group of memory cells arranged at similar locations in each unit group are connected in common to a word line selecting line selected by a select circuit. Therefore, the number of memory cells connected to one word line can be reduced to decrease the power consumption and to increase the operating speed, without increasing the wiring capacitance and the chip size.

Semiconductor memory device and its topography

An automatic information receiving terminal device in a character/graphic information network system including a videotex communication network or a public communication network (telephone network) is connected to an information center through the videotex or public communication network so that various items of image information from the information center can be received by the terminal device. The terminal device having an internal clock and a time setting unit. The terminal device can automatically receive or reproduce desired information at an each time preset by the time setting means, so that the terminal device can automatically be operated without manual intervention so as to give emergency information or the like timely to a number of people.

Videotext communication network with a receiving terminal that

This protected MOS transistor circuit has a p-type semiconductor substrate, VSS terminal, input MOS transistor, first resistor connected to the gate electrode of transistor, and MOS transistor which has a gate electrode connected to the VSS terminal and a current path connected between the VSS terminal and a junction of the first resistor and the gate electrode of the input MOS transistor. This protected MOS transistor circuit further has a second resistor connected in series with the first resistor, and pn-junction diode connected reversely between the VSS terminal and the junction of the first and second resistors.

Protected MOS transistor circuit

An integrated circuit includes an input buffer circuit and an output buffer circuit. The source voltage to the input buffer circuit and the output buffer circuit are supplied through bonding pads formed independently on a semiconductor chip, and electrically connected to a source potential lead pin. The input node of the input buffer circuit is coupled to the source potential of the output buffer circuit with a capacitor.

Integrated circuit with switching noise reduction by feedback

Growing community of inventors

Yokohama, Japan

Youichi Suzuki