Matsushita Electric Industrial Co., Ltd.

Youichi Nishida

Ikuo Fuchigami

Tomoo Kimura

Tomonori Kataoka

Satoshi Kohtaka

Jyunji Michiyama

Takashi Hashimoto

Ken Kawai

Hiroto Tomita

Masahiro Ohashi

Masatoshi Matsuo

An image processing unit decodes coded data that have been coded and synthesizes the decoded moving image with graphics data. In a case where only graphics data are to be displayed, a bypass unit outputs the graphics data to a display device without use of an image processing unit. A control unit performs control of the supplying of a power supply voltage and a clock to a region containing the image processing unit and performs control of the bypass unit. If processing at the image processing unit is unnecessary, the supply of a power supply voltage or the supply of a clock to the region containing the image processing unit is stopped so as to stop the region and enable reduction of wasteful power consumption.

Data processing system for reducing wasteful power consumption

A current sense amplifier circuit is provided with a reference current generator for generating a reference current according to the characteristics of a memory cell, and a current comparator, and the current comparator compares the memory cell current with the reference current. Thereby, the range of the operating power supply voltage is increased. Further, a current sense amplifier circuit is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell that is set in multiple states.

Current sense amplifier circuit

The present invention provides a semiconductor memory which can reduce the area of a circuit for replacing defective memory cells with redundant memory cells as well as reduce the time for writing defect information. The semiconductor memory of the present invention comprises a memory cell array,comprising (n&plus;1) (n is a positive integer) word lines, a register unit,holding an encoded defect address for specifying a defective word line, a defect address decoder,for decoding the defect address from the register unit,to specify the defective word line, selection means S,&tilde;Sn for selecting, for the i-th (1&lE;i&lE;n) output signal line of a row decoder,, one of the i-th and i&plus;1-th word lines and connecting the selected word line to the i-th output signal line, and control means C,&tilde;Cn each controlling corresponding one of the selection means S,&tilde;Sn on the basis of an output of the defect address decoder,so as to select, for the output signal line of the row decoder,, one of the word lines except the defective word line in accordance with the arrangement order.

Semiconductor memory having reduced time for writing defective information

A semiconductor integrated circuit includes a booster for boosting a power supply voltage, and outputting the boosted voltage; an output circuit being supplied with the boosted voltage, and generating an output voltage from the boosted voltage; a reference voltage generator being supplied with the power supply voltage, and generating a reference voltage from the power supply voltage; a voltage divider being supplied with the output voltage from the output circuit, and dividing the output voltage with a predetermined voltage ratio; and a differential amplifier being supplied with the reference voltage and the divided voltage, and controlling the output circuit by supplying the output circuit with a voltage obtained by performing differential amplification on the reference voltage and the divided voltage according to the power supply voltage, thereby maintaining the output voltage from the output circuit at a predetermined voltage. In this circuit, since the reference voltage generator and the differential amplifier are operated with the power supply voltage, it is not necessary to supply the boosted voltage to them, whereby the output current from the booster is reduced. Therefore, undesired reduction in the boosted voltage due to an increase in the output current is suppressed. As the result, the capacitance used in the booster is reduced, and the area of the semiconductor integrated circuit is reduced.

Semiconductor integrated circuit

Growing community of inventors

Fukuoka, Japan

Youichi Nishida