Mitsubishi Denki Kabushiki Kaisha

Youichi Ishimura

Yoshifumi Tomomatsu

Hideki Takahashi

Hiroshi Yamaguchi

Katsumi Satoh

Kazunari Hatade

Hideki Haruguchi

Norihisa Asano

In an insulated gate semiconductor device having first, second and third gate electrodes ( ) which are buried in first, second, and third trenches ( ), an emitter electrode ( ) is commonly connected to a base region ( ), an emitter region ( ) and the second gate electrode ( ), and the third gate electrode ( ) is connected to only the first gate electrode ( ). An insulating interlayer ( ) interposed between the emitter electrode ( ) and the gate electrodes ( ) has a pattern configuration such that the second gate electrode is partially connected to the emitter electrode, to thereby control a gate capacity and suppress a short-circuit current caused by a crack.

Insulated gate semiconductor device for realizing low gate capacity and a low short-circuit current

An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor ( ) is connected in parallel to a diode ( ) made of silicon carbide. Although a resistive component of the diode ( ) varies widely with turn-on and turn-off of the diode ( ), connecting the resistor ( ) in parallel to the diode ( ) allows suppression of variations in a resistive component of an LCR circuit formed by the diode ( ) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Silicon carbide semiconductor switching device

A semiconductor wafer and a semiconductor device with more chips are obtained. The semiconductor wafer includes a plurality of dicing lines (DXa, DXb, DYa, DYb) extending in the lateral direction (X) and in the longitudinal direction (Y) with an interval (L,) therebetween, and a semiconductor element forming region (CR,) with a semiconductor element, sectioned by the dicing lines (DXa, DXb, DYa, DYb). The dicing lines both in the lateral direction (X) and in the longitudinal direction (Y) have alternate widths (La, Lb), one of which (Lb) is larger than the other (La).

Semiconductor wafer and semiconductor device

An n,semiconductor region (,) is formed in a lower portion (,) of a p-type diffusion region (,) where a channel is created. The n,semiconductor region (,) is formed in a region extending from a one-side major surface of a semiconductor layer (,) up to the lower portion (,) of the p-type diffusion region (,). The impurity concentration of the n,semiconductor region (,) is determined higher than that of a n,semiconductor region (,). With this structure, it is possible to reduce an on-resistance without deteriorating a withstand avalanche voltage.

Field effect semiconductor device

It is an abject to stably and surely perform protection operation of devices. Since the gate threshold voltage V.sub.GE(th)S in a sense IGBT cell constituting a sensing circuit is set to have a higher value than the gate threshold voltage V.sub.GE(th)M in a main IGBT cell constituting a main circuit, a finite time .DELTA.t is required from when the gate voltage V.sub.GE reaches the gate threshold voltage V.sub.GE(th)M until when it reaches the gate threshold voltage V.sub.GE(th)S in the turn-on period. Accordingly, the rise of the main current Is of the sensing circuit is delayed from the main current Im of the main circuit. As a result, surge current does not appear in the current Is. As the surge current does not appear in the main current of the sensing circuit, a protection circuit of the device operates stably, and breakdown of the device is surely prevented.

Growing community of inventors

Tokyo, Japan

Youichi Ishimura