No. 24 Research Institute of China Electronics Technology Group Corporation

China Electronic Technology Corporation, 24th Research Institute

No. 24 Research Institute of China Electronic Technology Corporation

Youhua Wang

Gangyi Hu

Dongbing Fu

Guangbing Chen

Jie Pu

Ting Li

Ruzhang Li

Daiguo Xu

Liang Li

Xiaofeng Shen

Jian'an Wang

Yuxin Wang

Mingyuan Xu

Zhengping Zhang

Xi Chen

Xingfa Huang

Xueliang Xu

Jun Liu

Xianjie Wan

Tiehu Li

Ruitao Zhang

Junan Zhang

The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Circuit for generating multi-phase clock having random disturbance added thereto

The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.

Error compensation correction system and method for analog-to-digital converter with time interleaving structure

The present invention provides a device and method for correcting error estimation of an analog-to-digital converter. The method comprises: according to a preset initial value of a correction parameter, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to the initial value of a correction parameter, correcting a gain error between channels, generating a general correction signal, buffering the general correction signal and triggering a counting cell to start counting, and meanwhile calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting up to a preset value, setting enable ends of a low-pass filter accumulating cell and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching the error estimation result, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching the updated clock correction parameter and gain correction parameter, and resetting to carry out cyclic estimation correction. According to the present invention, in the case where a few effective sample points are used, the estimation accuracy is improved and the convergence rate of the estimation correction is increased.

Device and method for correcting error estimation of analog-to-digital converter

The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

High speed duty cycle correction and double to single ended conversion circuit for PLL

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Chongqing, China

Youhua Wang