Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Youhei Yamada

Masahiro Moniwa

Toshifumi Takeda

Yasushi Koubuchi

Koichi Nagasawa

Noriyuki Sakuma

Yoshio Homma

Seiichi Kondo

Takeshi Kimura

Hiroki Nezu

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Semiconductor integrated circuit device

Interconnections are formed over an interlayer insulating film which covers MISFETQformed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Semiconductor integrated circuit device including wiring lines and interconnections

In a polishing apparatus having a cover body with fluid pressing mechanism, during polishing, vibration and migration of sticking portion between a retainer and a membrane generated in downstream of rotation of a polishing platen is prevented by reducing sticking force between the retainer and the membrane to less than force needed to wafer polishing with rotation of the cover body.

Polishing apparatus

Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Growing community of inventors

Kodaira, Japan

Youhei Yamada