Nippon Telegraph and Telephone Corporation

Youhei Sakamaki

Kota Shikama

Shinsuke Nakano

Yuko Kawajiri

Salaheldin Ahmed Ezzeldin Ibrahim Mohamed

A signal processing circuit is provided that generates output signals to be output from spatially different output ports based on bit combinations of an input word consisting of a plurality of bit signals. A distributed memory, a ROM and a DAC in which the signal processing circuit is used are also provided. A recognition circuit includes a serial port to which a bit signal is input and 2output ports recognizing an input N-bit word and corresponding uniquely to 2bit combinations. Output ports of the recognition circuit are connected to 2input ports of an electric circuit. With no signal input to the recognition circuit, all outputs are constantly in a Low level state. In a case where a bit signal is input to the serial port of the recognition circuit, only one of the output ports corresponding to the bit combinations turns to a High level state.

Growing community of inventors

Atsugi, Japan

Youhei Sakamaki