Intel Corporation

Other

Youfeng Wu

Cheng C Wang

Mauricio Breternitz, Jr

Shiliang Hu

Edson Borin

Hongbo Rong

Hyunchul Park

Ho-Seop Kim

Sara S Baghsorkhi

Albert Hartono

Justin E Gottschlich

Herbert H Hum

Jaewoong Chung

Gilles A Pokam

Vineeth Mekkat

Ali-Reza Adl-Tabatabai

Cristiano L Pereira

Nalini Vasudevan

Wei Liu

Bratin Saha

Wei-Yu Chen

Tin-Fook Ngai

Jason M Agron

Oleg Margulis

Craig Buchanan Zilles

Li-Ling Chen

Robert Valentine

Christopher B Wilkerson

David J Sager

Koichi Yamada

Ron Gabor

Rajiv Gupta

Joseph Nuzman

Shlomo Raikin

Ruchira Sasanka

Bryan P Black

Sebastian Winkel

Suresh Srinivas

Jayaram Bobba

Peter Sassone

Omar M Shaikh

Dong-Yuan Chen

Jesse Z Fang

Leeor Peled

Howard Chen

Bixia Zheng

Sangwook Kim

Jason A Domer

Ali Reza Adl-Tabatabai

Ho-seop Kim

Hanjun Kim

Marcelo S Cintra

Alexandre Xavier DuChateau

Elmoustapha Ould-Ahmed-Vall

Christopher J Hughes

Rajesh M Sankaran

Milind Baburao Girkar

Tatiana Shpeisman

John Thomas Shen

Victor W Lee

Jeffrey J Cook

Dz-Ching Ju

Paul M Petersen

Arch D Robison

Kalyan Muthukumar

Ethan Schuchman

Daniel M Lavery

Rolf Kassa

Ryan N Rakvic

Anwar Ghuloum

Ching-Tsun Chou

Todd A Anderson

Girish Venkatasubramanian

Jeffrey P Rupley, Ii

Hideki Ido

Yong-fong Lee

Tyler N Sondag

Zhiwei Ying

Denis M Khartikov

Balaji Vijayan

Irina Calciu

Peng Tu

David A Berson

James Mason

James E Smith

Byoungro So

Janghaeng Lee

Hou-Jen Ko

Xipeng Shen

Hai Liu

P G Lowney

Jeffery J Cook

Aashish Phansalkar

Lixin Su

Joseph Blomstedt

Joao Paulo Porto

Vijayanand Nagarajan

Chengyan Zhao

Bolei Guo

Zhiyuan Li

Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.

Dynamic core selection for heterogeneous multi-core systems

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

A processor for redundant stores includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, a binary translator, and a memory execution unit. The binary translator includes circuitry to identify a first region of the instruction stream including a redundant store, mark a first starting instruction of the first region with a protection designator, mark a first ending instruction of the first region with a clear designator, and store an amended instruction stream with the markings. The memory execution unit includes circuitry to track the first redundant store based on the protection designator and the clear designator to eliminate the first redundant store.

Eliminating redundant stores using a protection designator and a clear designator

Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

A processor of an aspect includes a decode unit to decode a persistent store fence instruction. The processor also includes a memory subsystem module coupled with the decode unit. The memory subsystem module, in response to the persistent store fence instruction, is to ensure that a given data corresponding to the persistent store fence instruction is stored persistently in a persistent storage before data of all subsequent store instructions is stored persistently in the persistent storage. The subsequent store instructions occur after the persistent store fence instruction in original program order. Other processors, methods, systems, and articles of manufacture are also disclosed.

Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent stores

Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Methods and systems to identify and reproduce concurrency violations in multi-threaded programs using expressions

Embodiments described herein utilize restricted transactional memory (RTM) instructions to implement speculative compile time optimizations that will be automatically rolled back by hardware in the event of a missed speculation. In one embodiment, a lightweight version of RTM for speculative compiler optimization is described to provide lower operational overhead in comparison to conventional RTM implementations used when performing SLE.

Lightweight restricted transactional memory for speculative compiler optimization

Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

Systems, apparatuses, and methods for data speculation execution

A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.

Hybrid atomicity support for a binary translation based microprocessor

Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

Conjugate code generation for efficient dynamic optimizations

In an example, an apparatus includes a binary translator (BT) including circuitry to: analyze a code block; determine that an architectural register mapped to a physical register in the physical register file is available for early reclamation; and insert a reclamation hint into the code block. In another example, a processor reclaims the physical register based at least in part on the reclamation hint.

Register reclamation

In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

Optimized call-return and binary translation

A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

Eliminating redundant store instructions from execution while maintaining total store order

Growing community of inventors

Palo Alto, CA, United States of America

Youfeng Wu