University of Electronic Science and Technology of China

Electronic and Information Engineering in Dongguan, Uestc

Youbiao Zou

Bo Zhang

Zehong Li

Jinping Zhang

Wenlong Song

Xunyi Song

Hongming Gu

A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting Hions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.

Method for manufacturing vertical super junction drift layer of power semiconductor devices

Growing community of inventors

Chengdu, China

Youbiao Zou