Samsung Electronics Co., Ltd.

You-Sang Lee

Jin-Yub Lee

Yoon-Hee Choi

Sang-Won Hwang

Bo-Geun Kim

Joon Young Kwak

A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage.

Reference voltage generating circuit

Provided are a flash memory device and method of controlling certain program operation voltages. The flash memory device includes a high voltage generation circuit providing a high voltage to a block selection circuit and a program voltage to a row decoder. The high voltage generation circuit includes a charge pump, a high voltage control circuit controlling the charge pump to provide the high voltage, and a program voltage control circuit providing the program voltage in relation to the high voltage, wherein the high voltage control circuit and the program voltage control circuit operate in response to the same control code.

Flash memory device and programming method

A semiconductor device includes a plurality of fuses, and a plurality of latch circuits respectively electrically connected to the plurality of fuses. The plurality of latch circuits are configured to store respective fuse-cut information from the plurality of fuses, and to then sequentially transmit the fuse-cut information through the latch circuits to output sequential data indicative of a fuse-cut state of the plurality of fuses.

Semiconductor device and test system which output fuse cut information sequentially

A redundancy selector circuit for use in a non-volatile memory device include a ROM cell array, in which defective addresses are stored, including a plurality of ROM cells arranged in a matrix of rows and columns; a ROM controller for sequentially selecting rows of the ROM cell array at power-up; a sense amplifier block for sensing and amplifying data bits from ROM cells of the respective rows selected sequentially according to the control of the ROM controller; a latch block for receiving data bits sensed by the sense amplifier block through a switch circuit and latching the input data bits as a defective address; and a comparator block for detecting whether an address input in a normal operation matches one of the defective addresses stored in the latch block. As the rows are sequentially selected, the defective addresses of the ROM cell array are transferred to the latch block through the sense amplifier block by means of serial transfer.

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Seoul, South Korea

You-Sang Lee