Taiwan Semiconductor Manufacturing Comp. Ltd.

You-Ru Lin

Chih-Hsin Ko

Cheng-Hsien Wu

Clement Hsingjen Wann

Yi-Jing Lee

Chi-Yuan Shih

Shih-Fen Huang

Cheng-Tien Wan

Yan-Jie Liao

Chun-Ren Cheng

Yi-Chuan Teng

Yi Heng Tsai

Ching-Hui Lin

Fu-Chun Huang

Kai-Fung Chang

Hao-Hsiung Lin

Shu-Han Chen

Fan Hu

Yen-Wen Chen

Anderson Lin

Wei-Chieh Chen

Alexander Kalnitsky

Yu-Lien Huang

Tung Ying Lee

Shao-Ming Yu

Wei-Sheng Yun

Jen-Yuan Chang

Wen-Chuan Tai

Hsiang-Fu Chen

Chia-Ming Hung

Ivan Hua-Shu Wu

Sheng Kai Yeh

The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.

FinFET device having a channel defined in a diamond-like shape semiconductor structure

A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.

Semiconductor device and method of manufacture

In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.

Fatigue-free bipolar loop treatment to reduce imprint effect in piezoelectric device

In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Integrated heater (and related method) to recover degraded piezoelectric device performance

Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.

Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device

In some embodiments, the present disclosure relates to a method for recovering degraded device performance of a piezoelectric device. The method includes operating the piezoelectric device in a performance mode by applying one or more voltage pulses to the piezoelectric device, and determining that a performance parameter of the piezoelectric device has a first value that has deviated from a reference value by more than a predetermined threshold value during a first time period. During a second time period, the method further includes applying a bipolar loop to the piezoelectric device, comprising positive and negative voltage biases. During a third time period, the method further includes operating the piezoelectric device in the performance mode, wherein the performance parameter has a second value. An absolute difference between the second value and the reference value is less than an absolute difference between the first value and the reference value.

The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

Reduction of electric field enhanced moisture penetration by metal shielding

Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.

Semiconductor arrangement

Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.

A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.

Semiconductor device and method for manufacturing the same

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Taipei, Taiwan

You-Ru Lin