Mediatek Corporation

National Taiwan University

Ite Tech. Inc.

You-Ming Tsao

Shao-Yi Chien

Liang-Gee Chen

Chun-Liang Chen

Chih-Hao Sun

Yu-Ting Kuo

Chien-Nan Lin

Hsueh-Bing Yen

An-Li Wang

Ka-Hang Lok

Chen-Chia Lee

Yung-Hsin Chu

A computing system performs balanced power management based on requirements of graphics scenes in a video game. Based on the requirements of the graphics scenes, the system selects one or more performance metrics to reduce in real-time, where the performance metrics are indicators of video game quality. The system compares estimated power consumption with a power budget after reducing the one or more performance metrics. Based on the requirements of the graphics scenes, the system further selects one or more quality enhancers to activate in real-time while keeping the estimated power consumption within the power budget. Each quality enhancer enhances the video game with respect to a performance metric. The system then displays the video game enhanced by the one or more quality enhancers.

Adaptive loading-aware system management for balancing power and performance

An electronic device includes a memory controller and a processor. The memory controller controls access of a memory device. The processor performs a calibration operation to find a first setting range of a memory controller parameter under a first clock frequency of the memory device, to find a second setting range of the memory controller parameter under a second clock frequency of the memory device, and to determine a calibrated setting of the memory controller parameter according to an overlapped range of the first setting range and the second setting range.

Apparatus and method for controlling controllable clock source to generate clock signal with frequency transition

A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Method and apparatus for performing dynamic configuration

A method for performing dynamic configuration includes: freezing a bus between a dynamic configurable cache and a plurality of cores/processors by rejecting a request from any of the cores/processors during a bus freeze period, wherein the dynamic configurable cache is implemented with an on-chip memory; and adjusting a size of a portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for one of the cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

A graphic processing unit (GPU) with a configurable filtering module (CFU) and an operation method thereof are presented. The graphic processing unit comprises a memory module and a configurable filtering module. The memory module stores at least one texture image. The configurable filtering module, connected to the memory module, comprises a plurality of filter equations, from which a filter equation is selected. A plurality of pixel points are sampled from the texture image. Each sampled pixel point is set with a weight value respectively. Each sampled pixel point with a weight value corresponding thereto is substituted into the selected filter equation to perform an operational process to acquire an operated value. Thereby, the user can decide the operation method of the GPU by selecting an appropriate filter equation and setting adjustable parameters in the filter equation.

Graphic processing unit (GPU) with configurable filtering module and operation method thereof

A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number (N) of stream processing units, and the memory module is configured with a number (N) of memory bank units each corresponding to a respective one of the stream processing units. The memory module is reconfigurable based on a desired inter-level configuration so that each of the memory bank units is configured to have a memory size sufficient to meet processing requirement of the respective one of the stream processing units.

Stream processing system having a reconfigurable memory module

In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N&#x2267;2. When the scheduler receives a stream element from a Pstream fetching unit, the scheduler assigns a Pstream processing unit as a target stream processing unit when the Pstream processing unit does not encounter a bottleneck condition, assigns a Qstream processing unit, which does not encounter the bottleneck condition, as the target stream processing unit when the Pstream processing unit encounters the bottleneck condition, where 1&#x2266;P&#x2266;N, 1&#x2266;Q&#x2266;N, and P&#x2260;Q, and dispatches the received stream element to the target stream processing unit such that the target stream processing unit processes the stream element dispatched from the scheduler.

Multi-core stream processor having (N) processing units and (N+1) fetching units

An efficient system and method for adaptive tile depth filter (ATDF) is disclosed. The key concept of this system and method is to consider more occlusion conditions in order to achieve a better performance of filter before the conventional Z test process in three dimensional graphics pipeline. Two occlusion criteria, Zmax and Zmin (depth range in a tile), are introduced first for occlusion and non-occlusion fragments in a tile. The points between Zmax and Zmin are in uncertain fragment which may need to go through the later Z test. Moreover, a new technique, coverage mask, can further filter the points in the uncertain fragment to a final uncertain fragment and non-occlusion fragment. Besides, the coverage mask can be used to efficiently decide which tile needs the further sub-tile depth filter.

Growing community of inventors

Taipei, Taiwan

You-Ming Tsao