Mediatek Corporation

Mediatek USA Inc.

You-Min Yeh

Chin-Wang Yeh

Ching-Chieh Wang

Rong-Liang Chiou

Chang-Chu Liu

Chin-Wen Liang

Yu-Hsiung Deng

Sheng-Hsiang Chang

Kang-Yi Fan

Chien-Chung Chen

Hua Wu

Chih-Chieh Yang

Chien-Chung Huang

Tung-Hao Huang

Yuan-Liang Cheng

ShihHsin Tai

Chung-Yu Chang

The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Dynamic frame rate adjustment mechanism

A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.

Signal processing apparatuses capable of processing initially reproduced packets prior to buffering the initially reproduced packets

A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Packet processing apparatus and method capable of generating modified packets by modifying payloads of specific packets identified from received packets

A method for setting the bandwidth of a multiple stream decrypting and decoding system includes at least the following steps: authenticating a multiple transport stream decryption card; sending a transport stream through the system; extracting program information from the transport stream; utilizing the program information to set a bandwidth limit to the system; and enabling the multiple transport stream decryption card.

Multiple stream decrypting and decoding systems and related methods thereof

A dynamic polarity control method for driving an LCD is provided. Gray level information is obtained, which indicates gray levels of dots in an image to be displayed. The gray level information is applied to each of a plurality of polarity patterns to obtain a plurality of combined patterns, wherein each of the polarity patterns has an individual polarity distribution. The gray levels of each of the combined patterns are summed up. A final pattern is selected from the plurality of polarity patterns according to the summed results, to drive the LCD for displaying the image.

Dynamic polarity control method and polarity control circuit for driving LCD

A transport stream processing apparatus includes a demodulation module, a transport stream storage module, a multiplexer, and a conditional access system interface. The demodulation module is for demodulating an input signal to generate a first transport stream. The transport stream storage module is for storing a second transport stream. The multiplexer has an output port, a first input port for receiving the first transport stream, and a second input port for receiving the second transport stream. The multiplexer selectively couples the first input port or the second input port to the output port. The conditional access system interface is coupled to the output port of the multiplexer for coupling a conditional access module. The conditional access system interface transmits a transport stream outputted from the output port of the multiplexer to the conditional access module for signal processing when the conditional access module is coupled to the conditional access system interface.

Transport stream processing apparatus capable of storing transport stream before the transport stream is descrambled and then descrambling the stored transport stream for playback

A transport stream processing system capable of recording and playing back a transport stream carrying a plurality of transport stream packets is provided, and includes: a first memory unit storing a plurality of sets of control words; a packet identifier filter acquiring a set of control words according to a packet identifier value of a transport stream packet and configuring an indicator to indicate whether the transport stream packet is for a recording or a playback operation; a second memory unit storing a plurality of data structures, wherein each data structure corresponds to an index number of each set of control words; and a processor determining whether the recording or playback operation for the transport stream packet is performed for the transport stream packet according to the indicator, retrieving a data structure according to the index number corresponding to the acquired set of control words and performing the operation accordingly.

Transport stream processing system and related method thereof

A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

A system for decrypting multiple transport streams is disclosed. The system includes: a Multiple Transport stream Multiplexer (M-Mux), for receiving at least a first transport stream and a second transport stream, and outputting a resultant transport stream; a multiple transport stream decryption card for decrypting the resultant transport stream to output a decrypted transport stream; a Source Multiplexer (S-Mux) for receiving the decrypted transport stream from the multiple transport stream decryption card and the resultant transport stream, and outputting a final resultant transport stream; and a Multiple Transport Stream Processor (M-Processor) for receiving the final resultant transport stream, and sending the final resultant transport stream to a corresponding framer.

A combined digital TV decoding and optical recording system includes a transport stream demultiplexer to demultiplex at least one compressed multimedia stream from an MPEG transport stream having multiplexed compressed multimedia streams. A video encoder compresses a video stream to generate a second compressed video stream. A common system controller controls operations of the transport stream demultiplexer and the video encoder, and allocates portions of a memory to the transport stream demultiplexer and the MPEG video encoder based on respective memory requirements.

Video processing and optical recording using a shared memory

A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.

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Chi-Lung, Taiwan

You-Min Yeh