Samsung Electronics Co., Ltd.

You-Mi Lee

Seung-hoon Lee

Kyung-Woo Nam

Woo-Seop Jeong

Hee-Cheol Choi

Dong-young Chang

Geun-Soon Kang

An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two pads so that a predetermined fixed logic value is outputted by the input buffers while the respective at least two pads have a floating status. The logic operation circuit performs a logic operation on signals applied to the respective at least two pads via the input buffers, and outputs a resultant value to an internal circuit. When the input end of the semiconductor is used in a multi-chip package, the internal circuit may not be affected by the other pads that are not bonded to external pins, even though only one pad is bonded to an external pin.

Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same

A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.

Semiconductor memory having variable memory size and method for refreshing the same

Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

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Seoul, South Korea

You-Mi Lee