Macronix International Co., Ltd.

You-Liang Chou

Wen-Jer Tsai

Chun-Chang Lu

A memory device and a reading method thereof are provided. A second word line and a third word line are adjacent to a first word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells of the first word line. When a read error occurs, a re-read procedure is executed for some of the memory cells belonging to a state marginal group. The read procedure includes: applying a read voltage to the first word line; applying a first pass voltage to the second word line and the third word line. The re-read procedure includes: applying the read voltage to the first word line; applying a second pass voltage and a third pass voltage different from the first pass voltage to the second word line and the third word line respectively.

Memory device and reading method thereof

A memory device and a reading method thereof are provided. The memory device at least includes a first word line, a second word line and a third word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells connected to the first word line. A recognition procedure is executed in response to at least one memory cell has an error. A re-read procedure is executed on the memory cell. The recognition procedure includes: applying a pass voltage to the first word line; applying a recognition voltage to at least one of the second word line and the third word line. The re-read procedure including: applying a second read voltage to the first word line; and applying a second pass voltage to the second word line and a third pass voltage to the third word line.

A memory device is provided and includes a memory array. The memory array includes multiple strings, each of the strings including multiple memory cells and at least one compensation cell that are coupled in series to a corresponding one of multiple bit lines. In a read operation, the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current in the corresponding bit line to a current value. The resistance is associated with a number of programmed cells in the memory cells coupled to the corresponding bit line.

Memory device and an operation method thereof

A data recovery method is applied to a memory device which has a target memory cell, a target word line and an adjacent word line adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. In the data recovery method, a first program voltage is applied to the target memory cell through the target word line, and a second program voltage is concurrently applied to the adjacent memory cell through the adjacent word line.

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Taichung, Taiwan

You-Liang Chou