Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

You-Jen Wang

Shen-Iuan Liu

Chewn-Pu Jou

Fu-Lung Hsueh

Feng Wei Kuo

Feng-Wei Kuo

A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.

Method and apparatus for amplifying a time difference

Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

Method and system for time to digital conversion with calibration and correction loops

An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKby a natural number M to generate a first output signal CK/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKand the first output signal CK/M. The DCO generates a clock signal CKbased on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKfrom the DCO and divides the frequency of the CKby a bit number of the digital control signals to generate a feedback signal CKto the first frequency divider.

Growing community of inventors

Taipei, Taiwan

You-Jen Wang