Samsung Electronics Co., Ltd.

Yotam Platner

Omer Shabtai

Nathan Henri Levy

Ishay Goldin

Ran Vitek

Alexandra Dana

Netanel Stein

Tal Heller

Alon Intrater

Yaron Ukrainitz

David Tsidkiahu

Zuf Pilosof

Or Davidi

Techniques and apparatuses enabling high accuracy video object detection using reduced system resource requirements (e.g., reduced computational load, shallower neural network designs, etc.) are described. For example, a search domain of an object detection scheme (e.g., a target object class, a target object size, a target object rotation angle, etc.) may be separated into subdomains (e.g., such as subdomains of object classes, subdomains of object sizes, subdomains object rotation angles, etc.). Specialized, subdomain-level object detection/segmentation tasks may then be separated across sequential video frames. As such, different subdomain-level processing techniques (e.g., via specialized neural networks) may be implemented across different frames of a video sequence. Moreover, redundancy information of consecutive video frames may be leveraged, such that specialized object detection tasks combined with visual object tracking across consecutive frames may enable more efficient (e.g., more accurate, less computationally intensive, etc.) full domain object detection and object segmentation schemes.

Fast object detection in video via scale separation

The described techniques provide for an automated process of hardware design using main applications (e.g., use cases) and a modeling heuristic of a compiler. Hardware may be optimized and designed based on the knowledge of the compiler for the hardware and firmware information. For instance, a user may define constraints (e.g., area constraints, power constraints, performance constraints, accuracy degradation constraints, etc.) and the changes of compilation heuristics and hardware parameters may be optimized to efficiently achieve the user defined constraints. Accordingly, hardware configuration parameters may be optimized based on the neural network's compilation process (e.g., actual compiler constraints) and optimization of power, performance, and area (PPA) constraints (e.g., user defined constraints). Specific neural processor (SNP) hardware may thus be designed based on the optimized hardware configuration parameters (e.g., via modeling heuristics of its compiler and main applications informed via user defined constraints or PPA constraints).

Hardware architecture determination based on a neural network and a network compilation process

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Tel Aviv, Israel

Yotam Platner