Nec Corporation

Nec Compound Semiconductor Devices, Ltd.

Other

Anelva Corporation

Hideki Matsumra

Yosuke Miyoshi

Yasunobu Nashimoto

Hideki Matsumura

Atsushi Masuda

Akira Izumi

Shuji Nomura

Kazuo Sakurai

Shouichi Aoshima

Masaaki Kuzuhara

Kazunori Asano

Masashi Mizuta

Yasunori Mochizuki

Masahiro Tanomura

Hidenori Shimawaki

Fumio Harima

A heterojunction bipolar transistor of the present invention is produced from a wafer including a substrate and a collector layer of a first conductivity type, a base layer of a second conductivity type and an emitter layer of the first conductivity type sequentially laminated on the substrate in this order. First, the wafer is etched up to a preselected depth of the collector layer via a first photoresist, which is formed at a preselected position on the emitter layer, serving as a mask. Subsequently, the collector layer etched with at least the sidewalls of the base layer and collector layer, which are exposed by the first etching step, and a second photoresist covering part of the surface of the collector layer contiguous with the sidewalls serving as a mask.

Heterojunction bipolar transistor and method of producing the same

This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10 eV cm or less, which is brought by the above pre-treatment in the insulator film deposition process.

Method and apparatus for depositing a thin film, and semiconductor device having a semiconductor-insulator junction

A Schottky gate FET including a gate electrode having a gate extension, a drain electrode and a drain contact layer overlying a semi-insulating substrate, wherein the gate extension overlies at least part of the drain electrode and the drain contact layer. The vertical overlapping between the gate extension and the drain contact region prevents the current reduction to make the circuit module mounting the Schottky gate FET non-usable.

Schottky gate field effect transistor

A field effect transistor includes a semiconductor substrate with a channel layer being formed on its surface, a source electrode and a drain electrode formed at a distance on said semiconductor substrate, and a gate electrode placed between the source electrode and the drain electrode and making a Schottky junction with the channel layer. The gate electrode is provided with an overhanging field plate section and between the field plate section and the channel layer, there is laid a dielectric film. When the relative permittivity and the film thickness of the dielectric film are denoted by &isin; and t (nm), respectively, the following condition is satisfied 5&lE;&isin;<8, and 100<t<350.

Field effect transistor

A bipolar transistor is disclosed, that comprises a collector layer of first conduction type, a base layer of second conduction type, formed on the collector layer, a prevention layer, formed on the base layer, for preventing carriers from being recombined, an emitter layer of first conduction type, formed on a first part of the prevention layer, and a base electrode, formed on a second part separated from the first part of the prevention layer.

Heterojunction bipolar transistor having prevention layer between base and emitter

A CVD apparatus is provided, which is capable of cleaning the inside of a reaction chamber without affecting a catalyzer member after a CVD process is completed. This apparatus is comprised of a reaction chamber; a substrate stage located in the chamber, a substrate being placed on the stage; a catalyzer holder located in the chamber for holding a catalyzer member; the holder having an inner space in which the catalyzer member is fixed; the holder having an opening that communicates with the inner space and that faces toward the substrate placed on the stage; a shutter located in the chamber for closing the opening of the holder; a cleaning device for cleaning an inside of the chamber after a CVD process is completed; and a gas supply line for supplying a source gas into the inner space of the holder. When a film is formed on the substrate, the source gas is supplied into the inner space of the holder to generate an active species due to a catalysis of the catalyzer member, and the active species is supplied to the substrate placed on the stage through the opening of the holder. When the inside of the chamber is cleaned by the cleaning device, the substrate is taken out of the chamber and the opening of the holder is closed by the shutter, separating the catalyzer member located in the holder from an outside atmosphere of the holder.

CVD apparatus

To provide a fabrication method of compound semiconductor devices which can improve the problems of conventional MESFETs, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension, and easily restrain the emitter-size effect of conventional mesa type HBT without revising or complicating its epitaxial layer structure, a fabrication method according to the invention of a semiconductor device having a high-resistance film (,) covering a part of a surface other than electrodes (,and,) of the semiconductor device comprises a step of depositing the high-resistance film (,) by way of catalytic CVD. The fabrication method preferably further comprises a step of surface cleaning performed before the step of depositing for cleaning the surface of the semiconductor device by a gas including active hydrogen flowing on the surface. As for the high-resistance film, a material including no oxygen such as SiN is applied.

Catalytic deposition method for a semiconductor surface passivation film

A field control electrode 9 is formed over an insulating film 6 on a channel layer 2, between a gate electrode 5 and a drain electrode 8. Tantalum oxide (Ta.sub.2 O.sub.5), for example, may be used as the material for the insulating film 6.

Fet having non-overlapping field control electrode between gate and drain

This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 10.sup.12 eV .sup.-1 cm.sup.-2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Method for depositing a thin film

A multi-layer structure inserted onto an interface between a compound semiconductor region and a highly resistive material region includes an epitaxial silicon layer up to 1.5 nm thick in contact with the compound semiconductor region and an amorphous silicon layer from 1 to 10 nm thick in contact with the highly resistive material region and laminated on the epitaxial silicon layer.

Growing community of inventors

Tokyo, Japan

Yosuke Miyoshi