Elpida Memory, Inc.

Other

Yosuke Kawamata

Hajime Tanaka

Makoto Kitayama

Disclosed are a semiconductor device capable of reducing the number of program fuses used therein, and a fuse circuit selection method capable of reducing the number of program fuses. The semiconductor device includes: a fuse circuit () and an entire inversion fuse circuit (), each of which includes plural program fuses, and which store desired addresses based on cutting patterns of the plural program fuses, wherein the fuse circuit () and the entire inversion fuse circuit () are configured to be capable of storing addresses different from each other based on the same cutting pattern. As described above, since plural types of the cutting patterns of the program fuses exist even in the same address, the fuse circuit for use is appropriately selected, thus it is made possible to reduce the number of fuse elements to be cut as a whole. Thus, manufacturing cost of the semiconductor device can be reduced, and in addition, it is made possible to enhance reliability of the semiconductor device.

Semiconductor device employing fuse circuit and method for selecting fuse circuit system

A fuse detection method for reading out a program state of each fuse and generating a killer signal indicating the program state of the fuse; counting the program state indicated by the killer signal to obtain a count value; inputting an expected value for the program state of the fuse; and determining whether the count value coincides with the expected value by comparing the count value with the expected value.

Semiconductor memory device including fuse detection circuit to determine successful fuse-cutting rate for optical fuse-cutting conditions

There is provided a memory testing apparatus and a memory testing method, for testing a semiconductor memory having redundant cells. In addition to a plurality of main cell fail information memories for a main cell array in the semiconductor memory under test, one redundant cell fail information memory is provided for redundant cells in the semiconductor memory under test. An address synthesizing circuit receives respective comparison results outputted in parallel from a plurality of comparators, each of which compares an output signal outputted from a semiconductor memory under test with an expected value, and an address supplied to the semiconductor memory under test, and for synthesizing a redundant cell fail information memory address for the redundant cell fail information memory. When at least one of the comparison results outputted in parallel from the plurality of comparators indicates a &ldquo;fail&rdquo;, a control circuit writes fail information into the redundant cell fail information memory at the redundant cell fail information memory address thus synthesized, with the result that fail information represented by a plurality of fail information bits outputted from the plurality of comparators is written into one cell within the fail information memory with one writing access.

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Tokyo, Japan

Yosuke Kawamata