Intel Corporation

Yosuke Kanaoka

Rahul N Manepalli

Gang Duan

Jesse Jones

Yoshihiro Tomita

Leonel R Arana

Rajasekaran Swaminathan

Srinivas V Pietambaram

Dilan Seneviratne

Praneeth Kumar Akkinepally

Bai Nie

Jason M Gamba

Vishal Shajan

Kristof Darmawikarta

Omkar G Karhade

Robert Alan May

Nitin A Deshpande

John Stephen Guzek

Sri Ranga Sai Boyapati

Sanka Ganesan

Ram S Viswanath

Yonggang Li

Robert M Nickerson

Yikang Deng

Tarek A Ibrahim

Wei-Lun Kane Jen

Chong Zhang

Dingying David Xu

Nicholas S Haehn

Meizi Jiao

Jung Kyu Han

Sameer Paital

Hongxia Feng

Matthew L Tingey

Srinivas Venkata Ramanuja Pietambaram

Haobo Chen

Arnab Roy

Yi Li

Wei Li

Minglu Liu

Robin Mcree

Robin Shea McRee

Raquel De Souza Borges Ferreira

Hong Seung Yeon

A method for recognizing a reference point associated with a fiducial marker including the steps of: obtaining or receiving image data of the fiducial marker; determining the degree of which the image data of the fiducial marker is aligned with one or more reference images; of which if the degree of alignment is determined to be less than an acceptable threshold predicting a set of coordinates of the reference point associated with the fiducial marker; incorporating the set of coordinates with the image data to form a modified image data; and determining the degree of which the modified image data of the fiducial marker is aligned with one or more reference images.

Device and method for improved fiducial marker detection

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Embedded die microelectronic device with molded component

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Microelectronic structures including bridges

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Patternable die attach materials and processes for patterning

An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

Dielectric filler material in conductive material that functions as fiducial for an electronic device

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.

Die placement and coupling apparatus

Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

Package-on-package interconnect stiffener

Growing community of inventors

Phoenix, AZ, United States of America

Yosuke Kanaoka