Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Joled Inc.

Panasonic Intellectual Property Management Co., Ltd.

Yosuke Izawa

Naoji Okumura

Yutaka Nio

Masahiro Tani

Toshichika Sato

Shinya Ono

Kouhei Ebisuno

Toshiyuki Kato

Mika Nakamura

Hiroshi Kojima

Kazuyoshi Nishi

Takahisa Hatano

Takashi Osako

Yasuo Segawa

Tetsurou Nakamura

Takashi Koizumi

Kouichirou Fue

Maoji Okumura

Toshiohika Sato

Display device includes: a power supplying unit which outputs at least a high-side or low-side output potential; an organic EL display unit which includes pixels and receives power supply from the power supplying unit; two or more detecting lines for transmitting a high-side or low-side applied potential applied to two or more pixels; a relay unit which outputs the high-side or low-side applied potentials transmitted by the detecting lines, to output lines fewer in number than the detecting lines; and a regulating unit which regulates at least the high-side or low-side output potential to be outputted by the power supplying unit, such that any one of potential difference between a reference potential and the high-side applied potential from the relay unit, potential difference between the reference potential and the low-side applied potential, and potential difference between the high-side applied potential and the low-side applied potential reaches a predetermined potential difference.

Display device and display device driving method for causing reduction in power consumption

A display device includes: a power supplying unit which outputs at least one of a high-side output potential and a low-side output potential; a display unit in which pixels are arranged in a matrix and which receives power supply from the power supplying unit; a monitor wire arranged along a column direction of the pixels in the matrix, which has one end connected to at least one pixel inside the display unit, and is for transmitting the high-side potential to be applied to the pixel; and a voltage regulating unit connected to the other end of the monitor wire, which regulates at least one of the high-side output potential and the low-side output potential to be outputted by the power supplying unit, to set a potential difference between the high-side potential and the low-side potential to a predetermined potential difference.

Display device

N drivers convert n digital values into n voltages. N amplifiers amplify the n voltages, thereby generate n drive voltages. An amplifier voltage supply supplies an amplifier voltage for driving the n amplifiers. An amplifier voltage controller detects a maximum digital value among a plurality of digital values, and sets the amplifier voltage to a voltage value dependent on the maximum digital value.

Drive voltage generator

An organic electroluminescence display includes pixels in a matrix that each emits visible light. A data line driver supplies a video signal to each pixel. The video signal includes first and second frames corresponding to first-eye and second-eye image information. A scanning line driver distributes a scanning signal to each pixel for controlling a supply of the video signal. The display includes an emitter in an arrangement position of the pixels in the matrix. The emitter emits infrared light in a same direction as the visible light. The scanning line driver supplies a control signal to the emitter that indicates a switching timing between the first frame and the second frame, and causes the emitter to emit the infrared light based on the control signal for reception by eye glasses for controlling opening and closing of electronic shutters.

Organic electroluminescence display device, video display system, and video display method

A stereoscopic display apparatus includes: a plurality of light-emitting devices; a power supply line for supplying current to the light-emitting devices; a switching device provided on the power supply line; a glasses control circuit which generates a glasses control signal for setting, in a pair of shutter-type glasses, a non-viewable period in which both the right-eye image and the left-eye image are made non-viewable at the same time; and a power supply control circuit which generates a device control signal for setting, in the switching device, a voltage reduced period in which the voltage between the electrodes in the light-emitting device is reduced, in which the glasses control circuit and the power supply control circuit control the shutter-type glasses and the switching device, respectively, for setting the non-viewable period to be a period at least from a start to an end of the voltage reduced period.

Stereoscopic display apparatus and method for driving stereoscopic display apparatus

An organic EL display panel includes: a P-type drive transistor having a gate connected to a capacitor and a drain connected to an organic EL element; an N-type drive transistor having a gate connected to the capacitor and a source connected to the organic EL element; a first power source line for applying a first voltage to the P-type drive transistor; a second power source line for applying, to the N-type drive transistor, a second voltage higher than the first voltage. The P-type drive transistor has characteristics such that a first gate voltage value corresponding to a predetermined current value in current-voltage characteristics of the organic EL element is a minimum voltage of the data voltage, and the N-type drive transistor has characteristics such that a second gate voltage value corresponding to the predetermined current value is greater than a third gate voltage value corresponding to a minimum current value of the organic EL element.

Organic electroluminescence display panel and method of driving the same

A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center cart of a picture can be horizontally compressed A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position or the picture can also be changed.

Video signal compression apparatus for horizontal compression of a video

A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position of the picture can also be changed.

A video signal processing apparatus processes plural kinds of video signals and is used for displaying each one of the processed outputs of the plural kinds of video signals on the same screen. In the video signal processing apparatus, a memory used for a subtitle processing circuit and a memory used for a helper signal separation circuit are used in common by providing a switching means to switch according to an input video signal. A subtitle processing circuit magnifies a video signal with a letter box format such that a horizontally long picture is inserted in a picture with a 4:3 aspect ratio on a horizontally long screen with 2:1 or 16:9 aspect ratio. The helper signal separation circuit is used for receiving a television signal such as an EDTV 2 system which has a helper signal to improve picture quality.

Signal processing apparatus for plural kinds of video signals

The invention relates to a video signal memory equipment comprising a FIFO memory for storing video data of video signals, and a control unit for controlling writing and reading in the FIFO memory, wherein the control unit receives a horizontal synchronizing signal of video signal in video data writing action, writes a specified number of video data from the beginning of video data of brightness signals of the horizontal scanning period sequentially into the FIFO memory, and reads out the specified number of video data upon every input of horizontal synchronizing signal, in video data reading action, in the written sequence as video data of that horizontal scanning period, thereby storing and producing the video data of video signals, whereby video data of each horizontal scanning period of video signals are continuously written into the FIFO memory by every specified number of pieces from the beginning, and are read out by every specified number of pieces upon every input of horizontal synchronizing signal, and hence the video data of video signals can be read out by dividing in every horizontal scanning period, and therefore the address generating device for dividing the data in every horizontal scanning period is not needed in this video signal memory equipment.

Memory equipment for writing/reading a defective video signal in a FIFO

An apparatus for converting an input video signal to a modified video signal comprises a memory for storing data corresponding to the input video signal, an address signal generating device for reading data from the memory and an interpolating filter for interpolating the data read from the memory to obtain a modified video signal. The data are stored and read from the memory using a clock having a predetermined frequency. However, since the number of addresses being read in one horizontal display varies with the conversion rate of video signals, the length of one horizontal display of the modified video signal is different from that of the input video signal.

Video signal converting device and noise eliminator used therein

A small scale gain control circuit for controlling gain correction quantity is realized, using the configuration of an inverter, a subtraction circuit, a limiter, and a multiplication circuit. Gain correction quantity is controlled in such a way that in the gradation correcting apparatus a first constant fixes a value beyond which gain correction quantity is zero and a second constant fixes an inclination of the characteristics line.

Gain control circuit and gradation correcting apparatus

A gradation correcting apparatus, which can be effectively incorporated into various video devices, enables the display of a sub-display within the domain of main-display (i.e. Picture in Picture) and also enables automatic adjustment of each gradation of the display dependent on the characteristics of the respective input signal. By using both a window pulse and a main- and sub-display switching signal, gradation corrections of the displays are carried out such that either no gradation correction is applied to the sub-display or a proper correction is applied according only to the sub-display signal. In this apparatus, the luminance information related to the sub-display and the luminance information related to the main-display excluding that of the sub-display are independently inputted into a signal correction system, thereby allowing individual processing of this information. Moreover, since the signal delay caused by the arithmetic processing can be precisely compensated for by a delay device, the gradation corrections for the main- and sub-displays are exactly executed according to the respective luminance level information, thus realizing an easy-to-see Picture in a Picture.

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Ibaraki, Japan

Yosuke Izawa