Motorola Corporation

Yossi Amon

Moshe Tarrab

Natan Baron

Eytan Engel

Eran Pisek

A finite impulse response filter (,) has a data memory bank (,) for storing data vectors and a coefficient memory bank (,) for storing coefficient vectors. Filtering is done by multiplying data words by coefficient words, and summing the results. The finite impulse response filter (,) operates in different modes, according to the type of data vector and coefficient vector. In two modes of operation consecutive elements of the data vector (,) are stored in consecutive odd memory words (,) within the data memory bank (,). In other modes consecutive elements of the data vector are stored in consecutive memory words (,) in the data memory bank (,). Consecutive coefficient vector elements (,) are stored in the consecutive memory words (,) in coefficient memory bank (,), wherein coefficient elements can be stored in reverse or forward order. The data memory bank (,) is coupled to a data address generator (,) comprising of counter (,), two multiplexers (,), a XOR gate (,) and an AND gate (,).

Finite impulse response filter and method

The present invention relates to memory and methods for storing/retrieving data in/from the memory that is accessed by at least two distinct data uses of different actual word widths. A memory for storing addressable binary data comprises a data storage organized in rows and columns of bit array cells, row address decoder and driver for addressing a selected row of bit array cells, column drivers for driving selected columns of bit array cells, and a bus switch port for selectively transferring data between the data storage and a first data bus with a first bus word width p and a second data bus with a second bus word width q smaller than the first bus word width p.

Multi bus access memory

A parallel data structure and a dedicated Viterbi shift left instruction minimize the number of clock cycles required for decoding a convolutionally encoded signal in a data processing system (20) in software. Specifically, the data structure and Viterbi shift left instruction reduce the number of clock cycles required for performing an add-compare-select butterfly operation. The add-compare-select butterfly operation is included in a DO loop in a plurality of instructions for executing a Viterbi decoding algorithm, and is repeated a predetermined number of times, for choosing the best path through a trellis diagram.

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Tel Aviv, Israel

Yossi Amon