Qualcomm Incorporated

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Yossi Amon

Dimitri Akselrod

Michael Andreas Staudenmaier

Lior Amarilio

Sharon Graif

Vincent Aubineau

Nir Gerber

Assaf Shacham

Asaf Ashkenazi

Ben Levin

Eyal Segev

David Asher Friedman

Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

Device identification generation in electronic devices to allow external control of device identification for bus communications identification, and related systems and methods

A data processing system comprising at least a memory unit, a first client connected to the memory unit, and a second client connected to the memory unit is proposed. The first client may comprise a first memory access unit and an information unit. The first memory access unit may read data from or write data to the memory unit at a first data rate. The information unit may update internal data correlating with a minimum required value of the first data rate. The second client may comprise a second memory access unit and a data rate limiting unit. The second memory access unit may read data from or write data to the memory unit at a second data rate. The data rate limiting unit may limit the second data rate in dependence on the internal data. The first memory access unit may, for example, read data packets sequentially from the memory unit, and the information unit may update the internal data at least per data packet. A method of controlling access to a shared memory unit is also proposed.

Data processing system and method of controlling access to a shared memory unit

Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media are disclosed. In one aspect, a method for generating combined bus clock signals comprises detecting a start event by each master device of multiple master devices communicatively coupled to a shared clock line of a shared bus. Each master device samples a plurality of shared clock line values of the shared clock line at a corresponding plurality of transitions of a reference clock signal for the master device. Each master device determines whether the plurality of shared clock line values is identical. If the shared clock line values are identical, each master device drives a shared clock line drive value inverse to the plurality of shared clock line values to the shared clock line at a next transition of the reference clock signal for the master device.

Generating combined bus clock signals using asynchronous master device reference clocks in shared bus systems, and related methods, devices, and computer-readable media

An integrated circuit that includes a controller for defining a test path that comprises at least one test access port out of multiple test access ports characterized by further comprising at least one multi-bit bypass logic for bypassing at least one of the multiple test access ports and for affecting a length of the test path. Conveniently, the length of the test path remains substantially fixed regardless of changes in a configuration of the test path. A method for testing an integrated circuit, the method includes a stage of propagating test signals across a test path. Whereas the method is characterized by a stage of defining a configuration of the test path, whereas the test path comprises at least one components out of at least one test access port and at least one bypass access logic; whereas the at least one multi-bit bypass logic bypass at least one of the multiple test access ports and affect a length of the test path.

Integrated circuit and a method for testing a multi-tap integrated circuit

An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry. A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.

Integrated circuit and a method for secure testing

Growing community of inventors

Kiryat Tivon, Israel

Yossi Amon