Fujitsu Corporation

Yoso Igi

Fumiaki Tahira

Kenji Fujisono

Kazuo Sumitani

Keiko Kawasaki

Koji Eto

Hiroki Masuda

Keiko Yuki

A memory access control system which performs a DMA transfer and allows a central control unit to perform a specific, required software operation. A central control unit sets a flag after running the specific software operation. The DMA transfer includes a first phase and a second phase, the first phase being a first transfer between a main memory and a first buffer memory and then a successive, second transfer between the main memory and a second buffer memory. The second phase is a transfer between a respective buffer memory and an external memory. A first DMA controller requests the first phase and controls the transfer of the second phase from a respective buffer memory when a transfer of the first phase from the main memory to the respective buffer memory ends, and prohibits a request for the first phase when the first transfer ends during a transfer of the second phase from the second buffer memory. A DMA request controller controls the request for the first phase and prohibits a request when the second transfer of the first phase ends and cancels the prohibition of a request when the flag of the central control unit is set. In response to a request for the first phase, an external bus control unit halts the operation of the central control unit and performs the first and second transfers of the first phase.

Memory access control system which prohibits a memory access request to

A memory apparatus including a back board having a lower address side and an upper address side, and a plurality of memory cards installed on the back board. Each memory card comprises a lower address side detecting signal pin for determining whether that memory card is installed on the lower address side of the back board, capacity detecting signal pins for notifying other memory cards of the capacity of that memory card, address signal pins, connected to an address signal line, and an address assigning circuit. When a memory card is installed on the lower address side of the back board, the capacity detecting signal pins and address signal pins assign an address to that memory card starting from a minimum address on the lower address side, and assign and address to another memory card which is installed on the upper address side starting with an address following the maximum address of the memory card installed on the lower address side.

Memory apparatus comprising memory cards with a side detecting signal

A communication control device includes a transmission speed converting unit having a dual port video RAM containing a RAM and a SAM, and a control unit having a register for storing a data store leading address of the RAM, a register for setting the number of words stored in the SAM, and a CPU. When data are transmitted, a user issues a data transmission request to the CPU in the control unit. According to the request, the CPU reads data from one system at its data transmission speed to the RAM or the SAM of the dual port video RAM, internally transmits the data between the RAM and the SAM, and finally transmits the internally transmitted data to the other system at its data transmission speed. The dual port video RAM absorbs the difference between the data transmission speeds of these two systems, and permits the data transmission at a lower cost than when using a FIFO memory and at a higher speed than when using a buffer memory.

Communication control system

A multiprocessor system is provided with main processors and secondary processors, and the processors are duplexed to form an active system and a standby system. A right to switch the system is given only to the main processors, and the secondary processors are operative to switch the system in accordance with the related system switching command, wherein data and control information are independently communicated between the main processors and the corresponding secondary processors belonging to the same active or standby system.

System for switching between processors in a multiprocessor system

A bus control system for controlling intermultiprocessor communication by polling, comprising a listener response signal line for transferring an end answer signal from a listener circuit to a talker circuit immediately when the transfer of data between the talker and the listener is finished, without waiting for the completion of data transfer within the receiving processor, whereby the bus occupation period is shortened.

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Kawasaki, Japan

Yoso Igi