Sanyo Semiconductor Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Electric Co., Ltd.

Yoshiyuki Yamagata

Tetsuya Tokunaga

Yasuo Osawa

Kensuke Goto

Hiroyuki Arai

Takeshi Kimura

A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.

Data processing circuit and data processing method

This invention offers an LCD drive circuit that prevents conversion to a wrong duty driving state and an unintended display caused by taking in of serial data corresponding to the wrong duty driving state. The LCD drive circuit is provided with an LCD drive signal generation circuit that generates driving signals to turn LCD segments on and off based on serial data received by a serial data receiving circuit and is switchable between a &#xbc; duty driving state and a &#x2153; duty driving state. The LCD drive circuit is also provided with a driving state setting circuit that sets the LCD drive signal generation circuit to the &#xbc; duty driving state based on identification data when the serial data receiving circuit receives the serial data corresponding to the &#xbc; duty driving state and thereafter forbids the LCD drive signal generation circuit to take in serial data corresponding to the &#x2153; duty driving state when the serial data receiving circuit receives the serial data corresponding to the &#x2153; duty driving state.

Liquid crystal display drive circuit

A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.

Data output circuit

This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.

Noise-tolerant data communication system

A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (&#x3c;m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m&#x2212;n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.

Growing community of inventors

Gunma-ken, Japan

Yoshiyuki Yamagata