Fujitsu Corporation

Yoshiyuki Suehiro

Masato Igarashi

Mitsugu Naitoh

Masayuki Naganuma

A semiconductor circuit comprises basic cells formed in an internal cell region on an integrated-circuit chip and pads for input/output cells, the pads being arranged in peripheral regions on said chip. The semiconductor circuit further comprises first logic circuit means provided for each of the input/output cells, each including logic circuits formed by transistors of relatively high drive capability which are a part of said respective input/output cells, the first logic circuit means being positioned in the perpheral regions. The present invention also comprises second logic circuit means provided for each of the input/output cells, each including remaining logic circuits of the respective input/output cells, the second logic circuit being formed by the basic cells formed in the internal cell regions, so that each of said input/output cells is formed by one pad and the combination of the first and second logic circuit means.

Semiconductor device

A master slice type integrated circuit for providing various circuits by altering the routing of interconnections comprises a plurality of input/output cells arranged in a peripheral region on a semiconductor chip, the input/output cells each comprising pads for connection with an external circuit, input wiring regions each for accommodating input interconnecting lines transmitting input signals applied to the pads, and output circuit regions each for forming output buffers; and a plurality of basic cells being arranged in a region on the chip surrounded by the arrangement of the input/output cells. Two adjacent input/output cells are paired with each other. The output circuit regions of the pair of the input/output cells are arranged in the vicinity of a boundary of the pair. The input wiring regions of the pair are arranged in the vicinity of boundaries with respect to other pairs.

Master slice type integrated circuit

A gate array integrated circuit incorporating memories and a method therefore can realize various bit/word constructions according to customer's requests. The gate array integrated circuit of the present invention provides a basic cell array region in which a plurality of basic cells are arranged, a memory cell matrix region in which a plurality of memory cells are arranged, and a plurality of peripheral circuits which include address input circuits and decoders to access the memory cells.

Gate array integrated circuit device and method thereof for providing

In a semiconductor device comprising a memory cell array and a test pattern generating circuit, the test pattern generating circuit generates the test pattern and transmits the test pattern to the memory cell array when receiving the least significant bit signal of address signals supplied to the memory cell array and the control signal.

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Kawasaki, Japan

Yoshiyuki Suehiro