Kabushiki Kaisha Toshiba

Yoshiyuki Shioyama

Hidenori Shibata

Masako Hori

Nobuo Nakamura

Hirofumi Yamashita

Ikuko Inoue

Tetsuya Yamaguchi

Hidetoshi Nozaki

Hisanori Ihara

Hiroshi Naruse

Akiko Nomachi

Hideki Inokuma

Akira Makabe

Seigo Abe

Hiroshi Matsushita

Kenichi Kadota

Kenji Kawabata

Takashi Sato

Takashi Sakamoto

Yutaka Koshino

Tatsuhiko Higashiki

Kazumasa Sunouchi

Ichiro Mori

Koji Kimura

Masaaki Ogawa

Takuya Kouno

Noboru Yokoya

Ai Omodaka

Seiichi Takedai

Thoru Ozaki

In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations. The three-dimensional shape combining processing unit creates a three-dimensional structure from the acquired one-dimensional film configurations on the basis of information on the intersection.

Simulation apparatus, simulation method and non-transitory computer readable recording medium

A defect analyzing method includes acquiring a position and a size of a defect obtained in a defect inspection of a semiconductor device and a waveform of a reflected light in a region which includes the defect, the waveform being obtained in an optical inspection; acquiring process step information which includes a plurality of process steps to manufacture the semiconductor device and a processing content per the process step; performing a process simulation of the semiconductor device based on the position and the size of the defect and the process step information; performing an optical simulation on a result of the process simulation thereby to generate a waveform of a reflected light; calculating a similarity degree between the acquired waveform of the reflected light and the generated waveform of the reflected light; and judging whether or not the calculated similarity degree exceeds a threshold value registered in advance.

Defect analyzing method and defect analyzing apparatus

A failure analysis method according to the invention includes inputting the positions of failures in multiple wafers of an input device; preparing multiple sections in the multiple wafers; calculating feature amounts, which are represented by at least one numerical value representing a distribution of the failures in the multiple wafers, for each of the multiple sections; and representing by a first numerical value, the degree of similarity between the multiple wafers in terms of the feature amounts. Subsequently, the method includes detecting another wafer, which has the first numerical value greater than a predetermined first threshold, for each of the multiple wafers and forming a similar wafer group of multiple wafers with similar distributions of the failures.

Method for analyzing fail bit maps of waters and apparatus therefor

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a pdiffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the pdiffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the pdiffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the pdiffusion layer to a position below the gate electrode.

Solid-state image pickup apparatus

A design system of an alignment mark for manufacturing a semiconductor device includes a memory which stores at least mark data including pattern information regarding plural kinds of marks and process data including condition information of manufacturing processes, and a first process simulator which simulates a substrate structure before patterning based on the process data, the substrate structure being formed in an identified manufacturing process. Moreover, the design system includes a second process simulator which simulates a processed shape of an identified mark after the patterning based on the simulated substrate structure and the process data, the mark formed in the manufacturing process, a signal waveform simulator which simulates a detection signal waveform of the mark, the waveform being obtained from the simulated processed shape of the mark, and a signal evaluation device which evaluates a suitability of the mark for the identified manufacturing process based on the simulated detection signal waveform.

Design system of alignment marks for semiconductor manufacture

A failure detection system includes a wafer test information input unit which acquires pass/fail maps for wafers for a plurality of types of semiconductor devices, displaying failure chip areas based on results of electrical tests performed on chips; an analogous test information input unit which classifies the electrical tests into analogous electrical tests with regard to analogous failures among the semiconductor devices; a subarea setting unit which assigns subareas common to the types of semiconductor devices on a wafer surface; a characteristic quantity calculation unit which statistically calculates characteristic quantities based on a number of the failure chip areas included in the subareas for each analogous electrical test; and a categorization unit which obtains correlation coefficients between the characteristic quantities corresponding to the subareas, and classifies clustering failure patterns of the failure chip areas into categories by comparing the correlation coefficients with a threshold.

Failure detection system, failure detection method, and computer program product

The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p diffusion layer and the drain. The position of an end of the signal accumulating section adjacent to the gate electrode of the MOS transistor extends over the end of the reading gate electrode of the p diffusion layer to a position below the gate electrode.

In a high density solid-state imaging device, of four charge transfer electrodes formed on a semiconductor substrate via a gate insulating film, a first electrode, a fourth electrode, and a part of a second electrode are made of a first conductive film, and a third electrode and the remaining portion of the second electrode are made of a second conductive film. In the second electrode, the first conductive film is joined to the second conductive film. An oxidation film formed by thermally oxidizing the first conductive film isolates the first electrode from the second electrode, the second electrode from the third electrode, and the third electrode from the fourth electrode. The end of the second conductive film is formed so as to locate on the oxidation film on the first conductive film.

Solid state imaging device with four-phase charge-coupled device and method of manufacturing the same

Solid-state imaging device and method of manufacturing the same

At the front side of a wafer cassette fitted to a wafer feeding unit of a magnetic levitation wafer conveying device, a wafer stopper for preventing the wafer waiting in the wafer cassette from popping out is provided. The wafer supplied from the magnetic levitation conveying device is supplied into the reaction chamber by magnetic force, and is directly held in the reaction chamber by this magnetic force. Since the wafer stopper is positioned between the wafer cassette fitted in the wafer feeding unit and the starting end of the wafer conveying route, the wafer waiting in the wafer cassette next to the wafer to be conveyed is prevented from popping out together with the wafer to be conveyed. Moreover, the wafer conveyed by the magnetic force can be directly held in the reaction chamber in heated state.

Apparatus for conveying and processing a wafer in a physically

According to the present invention, there is provided a solid-state imaging device that has a two-layer transfer electrode structure and is based on a four-phase driving all-pixel reading scheme. The transfer gate electrodes for taking the signal charges out of the photodiode PD and transferring them vertically are formed so that the polysilicon electrodes of a first layer and the polysilicon electrodes of a second layer may each have a specific gate length and be in contact with the gate insulating film on a silicon substrate. If four-phase transfer clocks are .phi.1 to .phi.4, the clocks will be applied to the transfer gate electrodes 31, 32 repeatedly in this order for a single pixel (photodiode PD): the second-layer electrode (.phi.2)--the second-layer electrode (.phi.3)--the first-layer electrode (.phi.4)--the first-layer electrode (.phi.1).

Four-phase driving CCD solid-state imaging device with a two-layer

A charge coupled device, together with a method for manufacturing the device, is provided which can eliminate a conventional problem, that is, the remaining of a light-receiving film at a great step area and a consequent lowering of a sensitivity resulting from the shutting-off of a portion of incident light. In the charge coupled device, insulating areas are formed in substantially strip-like array on a silicon substrate. Respective transfer electrodes are formed on a gate insulating film on a semiconductor substrate with an insulating areas interposed. The respective phase transfer electrodes are electrically separated by the insulating area. By doing so, the respective phase transfer electrodes can be formed on the same plane without leaving a greater step. This can achieve a thinned light shielding film.

Solid state image sensor device with single-layered transfer electrodes

A dynamic RAM array comprises a substrate, a plurality of semiconductor island regions and a trench region formed on the substrate, each island region being surrounded by the trench region, and the trench region having wider trench portions and narrower trench portions, an insulating layer formed on the trench region, capacitors refilled in the wider trench portions, each capacitor having a plate electrode, a capacitor insulating layer and a storage node electrode, refilled layers formed in the narrower trench portion, for forming field isolation regions, MOS transistors formed on the island region, each MOS transistor having a source, a drain and a gate as word line, one of the source and drain being coupled with the storage node electrode, and bit lines perpendicular to the word line, being coupled with the other of the source and drain.

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Kawasaki, Japan

Yoshiyuki Shioyama