Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Microcomputer Engineering, Ltd.

Yoshiyuki Miwa

Yasushi Akao

Terumi Sawase

Shigeki Masumura

Kunihiko Nakada

Haruo Keida

Hajime Yasuda

Tsuyoshi Jouno

Shiro Baba

Hideo Nakamura

Yuji Sato

Kazuo Naito

Tatsuya Aizawa

An output gate means is provided which is capable of outputting individual signals selectively to an internal bus; the individual signals are interchanged among a plurality of functional modules connected to the internal bus which is interfaced with an external circuit. An input gate means is provided which is capable of supplying selectively a signal, input to the internal bus, to a specified functional module in place of an individual signal.

Semiconductor integrated circuit device with test mode for testing CPU

A single-chip microcomputer includes a microprocessor, a subprocessor for performing peripheral functions, an external port for controlling an input/output operation from/to an external device and a multi-functional logic-in-memory for inputting a plurality of data from at least one of the microprocessor, the subprocessor and the external port and selecting write data from among the plurality of data in accordance with predetermined priorities.

Single-chip microcomputer having a memory including a one-bit memory

A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.

Microprocessor and method for setting up its peripheral functions

Growing community of inventors

Kawasaki, Japan

Yoshiyuki Miwa