Nec Corporation

Yoshiyuki Miki

Yasushi Ooi

A data processor which includes at least a central processing unit adapted to execute virtual memory management. The central processing unit internally includes a translation lookaside buffer (TLB) for translating a given virtual address into a corresponding real address. The TLB also generates a distinction signal indicating whether the translated real address designates a main memory or an external input/output device. In response to the distinction signal, a control signal generator outputs a set of input/output control signals for the access of the type designated by the distinction signal.

Data processor which efficiently accesses main memory and input/output

A Direct Memory Access (DMA) controller (1) of a 2-bus cycle transfer type executes a read cycle first to fetch data from a data source then internally rearranges or aligns the fetched data in accordance with a bus width and/or a storing address of a data destination unit and thereafter executes a write cycle to write the rearranged data in the data destination unit. The DMA controller includes a data register (106) having first and second fields (106-1 and 106-2). Data from the data source is temporarily stored in one of the first and second fields of the data register during the read cycle, and data in the other of the first and second fields is written to the data destination unit during the write cycle.

Growing community of inventors

Tokyo, Japan

Yoshiyuki Miki