Nec Electronics Corporation

Yoshiyuki Katou

Satoshi Yamamoto

Hideo Inaba

Atsushi Nakagawa

Takuya Hirota

Masahiro Yoshida

Masatoshi Sonoda

Noriaki Komatsu

Shouzou Uchida

The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell arrayThen, a test signal TEis set '1' to set a device in a test mode. Refresh addresses for test are then stored in a data store circuitA first address for test is applied to an address terminalwhereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell arrayare checked to decide the presence or absence of any abnormality.

Semiconductor memory device and its test method as well as test circuit

A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S, Sare divided into respective four blocks B&#x2dc;Band B&#x2dc;B. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Semiconductor storage and its refreshing method

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Kanagawa, Japan

Yoshiyuki Katou