Matsushita Electric Industrial Co., Ltd.

Yoshiyuki Iwamura

Fumio Sumi

Hiroshi Sakamoto

Motohide Nishibata

Noriyuki Manabe

Takashi Ishida

Shuichi Takayama

Kazushi Yamamoto

Toshinori Maeda

Yoshio Nakano

Toru Kakiage

Junko Sayama

Yoshihiko Imai

Makoto Ando

Shoji Nagata

The optical disk controller of this invention that reduces the frequency of output of status reports to relieve the burden of a system controller includes: a status generator for generating status reports each representing the operation state of the optical disk controller every sector of a disk; and a status sampling section for sampling the status reports at a set sampling interval. When a generated status report matches with 'sampling abort' status stored in a sampling category storing portion, status sampling is aborted.

Optical disk controller which sets sampling interval according to rotational speed of optical disk

In modifying a program fixedly recorded in a ROM or the like, desired positions in the program can be modified with a little hardware. In order to achieve the object, the program modification device comprises the modifying address register which stores the addresses of program data to be modified prior to the execution of the data and the modifying address storage table which stores all the addresses of the modification source programs to be loaded to the modifying address register and all the addresses of the modification target programs in pairs, and further comprises a modification target program having instructions embedded therein so as to load necessary information from the modifying address storage table to the modifying address register before the program to be modified is executed.

Program modification device

In the memory exclusive control device having a CPU-,accessible to both a common memory and first memory devices, the CPU-,is prohibited from accessing to the common memory device (,) during OFF state of an access permission flag, and when the access permissive flag ON is established by TCS (,), the gate of the access permitting unit (,) is opened to thereby permit the CPU-,to access to the common memory device (,). Thus, the memory exclusive control can be realized for transferring a desired program to be processed to the address space of the first memory device, allowing omission of a third memory device.

Memory exclusive control device and method therefor

A debugging apparatus is disclosed which verifies a program to be embedded into a target machine by running the program in an environment which is one or the target machine, an emulator, and a simulator. Each environment includes operation state information of the program and inputs and outputs the operation state information in a form unique to the environment. The debugging apparatus includes; target environment storing unit for storing an identification name of the target environment; receiving unit for receiving a command from an operator; instruction detecting unit for detecting a certain instruction in the command; specifying unit for, when the certain instruction is detected, specifying a target environment specified by the identification name as a source target environment and for specifying any of the rest of the environments as a destination target environment; reading unit for reading operation state information from the source target environment; converting unit for converting the operation state information into operation state information written in a form unique to the destination target environment; setting unit for setting the converted operation state information in the destination target environment; and operation resuming unit for resuming the operation of the program in the destination target environment.

Debugging apparatus for debugging a program by changing hardware

A program development system in which the debugging apparatus is informed of all of the optimization processes which have been performed. A primitive storage unit stores record information for the optimization processes. The input unit receives an input of a variable and a value, or an input of a line where execution is to be halted. The primitive combining unit obtains record information showing the optimization processes. The code execution unit executes the execution code. The variable operation unit obtains the value of a variable based on relations between variables and resources. The output unit displays the obtained value of the variable. The line display unit displays the program or the generated execution code. The line information display unit displays, in line units, information relating to the optimization performed for each line, The operation-possible variable display unit displays, for each line, variables which can be set and referred to in the line. The optimization process display unit shows how the optimization affects each variable.

Debugging information generation system

An information recording/reproducing apparatus for an information storage medium comprising sectors each having a data area composed of a read-only data area and a writable data area. Data in the read-only data area are formed through pressing or the like, and when the data in the read-only data area are to be renewed, renewed data are recorded in the writable data area so that it is made possible to form a large quantity of correctable read-only data.

Growing community of inventors

Osaka, Japan

Yoshiyuki Iwamura