Sanyo Electric Co., Ltd.

Yoshiyuki Ishizuka

Yukihiro Noguchi

Shigeharu Matsushita

Naofumi Sakai

Shinichi Takatsuka

Shoichiro Matsumoto

Takeshi Nakashima

Daisuke Ide

Hideaki Miyamoto

Naoya Sotani

Toru Dan

Isao Hasegawa

Takehito Ike

Takashi Goto

Hiroaki Furukawa

Kenji Uchihashi

Mitsuaki Harada

Hiroto Nagano

Takeshi Sakai

Tatsuro Gueshi

Satoru Ogasahara

Yasutaka Kobayashi

A display device includes a plurality of sub-pixels configured to display a plurality of colors including white. Each of the sub-pixels includes a self-luminous element configured to emit light by receiving supply of electric current, an input unit configured to input a luminance signal for determining luminance of the self-luminous element into the sub-pixel, and a control unit configured to control the supply of electric current to the self-luminous element. An area of light emission in each of the sub-pixels for the white is larger than an area of light emission in each of the sub-pixels for the other colors.

Display device

A secondary battery storage system rack is provided comprising a circuit block which is connected to an electric power line for exchanging electric power with the outside, a secondary battery block which is connected to the circuit block and which has a larger mass than the circuit block, and a storage body unit which stores, in the inside, the circuit block and the secondary battery block, wherein the secondary battery block and the circuit block are placed in one line along a direction of gravitational force, with the secondary battery block placed below the circuit block.

Secondary battery storage system rack with fire extinguisher device

A display capable of inhibiting a transistor from an instable operation resulting from fluctuation of the potential of a shielding film and suppressing occurrence of a malfunction is provided. This display comprises a first region including a first transistor, a first shielding film provided on the first region, arranged on a region corresponding to the first transistor and supplied with a first potential, a second region including a second transistor and a second shielding film provided on the second region, arranged on a region corresponding to the second transistor and supplied with a second potential.

Display capable of inhibiting instable operation of a transitor resulting from fluctuation of the potential of a corresponding shielding film

A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

Memory

A memory capable of suppressing disturbance is provided. This memory activates each of a selected word line and a bit line corresponding to unrewritten storage means while keeping potential difference therebetween at a level not more than a prescribed value and differentiates the length of a period for applying a voltage for rewriting to each of the selected word line and a bit line corresponding to rewritten storage means from the length of a transition period of the potential of at least either the word line or the bit line corresponding to the unrewritten storage means when performing a rewrite operation on partial selected storage means or performing no rewrite operation on all selected storage means.

A memory device capable of improving the degree of integration and effectively preventing false data reading is obtained. This memory device comprises a pair of bit lines extending in a prescribed direction, a word line arranged to intersect with the pair of bit lines and a memory cell, arranged between the pair of bit lines and the word line, consisting of two capacitance elements. Thus, the area of the memory cell is reduced and no reference voltage is required.

Memory device

A gate insulating layer and a first lower electrode are formed on a channel region of a silicon substrate, and an interlayer insulating film is formed on the silicon substrate so as to cover the first lower electrode and the gate insulating film. A buffer layer is formed on the interlayer insulating film, and a contact hole is formed in the interlayer insulating film and the buffer layer on the first lower electrode. A connecting layer and a second lower electrode are formed in the contact hole. A ferroelectric thin film and an upper electrode are formed in this order on the buffer layer so as to be brought into contact with the upper surface of the second lower electrode.

Dielectric device, dielectric memory and method of fabricating the same

Growing community of inventors

Inazawa, Japan

Yoshiyuki Ishizuka