Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Vlsi Limited

Yoshiyuki Ishida

Yasushige Ogawa

Masato Matsumiya

Hajime Sato

Satoshi Eto

Kuninori Kawabata

Mitsuhiro Nagao

Hiroyuki Sugamoto

Eisaku Itoh

Kohji Shimbayashi

Satoshi Takashima

Shouji Sakuma

An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced.

Semiconductor integrated circuit

A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.

Wafer structure with a plurality of functional macro chips for chip-on-chip configuration

It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating sectionin which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing sectionas an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section. Further, the judgment signal JG is outputted as digital signal through an external terminal Tand an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section. Consequently, the analog signal can be adjusted as analog value without being outputted outside and an adjustment test can be carried out with a simple tester device and according to a simple test method accurately and rapidly.

Semiconductor integrated circuit device, and adjustment method of semiconductor integrated circuit device

A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

Semiconductor device having logic circuit and macro circuit

Semiconductor device including logic circuit and macro circuit which has a function for stopping a direct current

A semiconductor integrated circuit that acquires an external signal precisely in a high speed operation. The semiconductor integrated circuit includes an internal circuit for acquiring an external signal in response to an address acquisition signal. A first holding circuit is connected to the internal circuit to hold the external signal for a predetermined period in response to a holding signal and provide the held external signal to the internal circuit. A control circuit is connected to the first holding circuit to generate the holding signal using the address acquisition signal.

Semiconductor integrated circuit having enhanced acquisition of external signal

A system LSI circuit which includes multiple memory circuits and functional logic circuits includes a control circuit for controlling the voltage supplied to the memory circuits. The control circuit includes trimming circuits for adjusting the memory supply voltages to ensure that the supplied voltages are within predetermined tolerances. The control circuit services all of the memory circuits, such that redundant logic functions are consolidated and multiple pads are not required to measure the memory supply voltages.

Trimming circuit for system integrated circuit

A semiconductor memory device, such as a SDRAM, includes input/output data line pairs, data bus line pairs, and a redundancy data bus line pair. The input/output data line pairs are connected to a corresponding one of the data bus line pairs and an adjacent one of the data bus line pairs via redundancy shift switches, with a last one of the input/output data line pairs being connected to a last one fo the data bus line pairs and the redundancy data bus line pair. Sense buffers and write amplifiers are connected between each of the data bus line pairs and the redundancy data line pair. The shift switches are located closer to the input/output data line pairs than the sense buffers and the write amplifiers so that data read from the memory cells is less effected by the on resistance and the parasitic capacitance of the switches. When the switches are located closer to the data bus lines than the sense buffers and the write amplifiers are, the switches effect the data signals of data read from the memory cells.

Semiconductor memory device having redundancy unit for data line compensation

A semiconductor memory device is disclosed that reduces a consumed current in a standby mode including a self-refresh mode. In one aspect of the invention, a semiconductor memory device includes a row-system circuit for receiving a first power from a power supply and operable in accordance with a row address strobe signal, a column-system circuit operable in accordance with a column address strobe signal, and a switch circuit that is connected to the column-system circuit. This switch circuit receives the first power from the power supply and supplies the first power to the column-system circuit in an active mode and produces a second power lower than the first power and supplying the second power to the column-system circuit in a standby mode.

Semiconductor memory device

A semiconductor memory device for serially outputting previously loaded data from an integral memory is disclosed herein. The device is configured to output head data from a predetermined location in the memory by latching the head data directly from a common bus. In a preferred embodiment the head data is latched by a single latch circuit. In a method of the invention, the head data is transferred directly from a predetermined memory address onto a common bus. A latch circuit then latches the head data from the common bus. The latched head data is next presented to an output buffer. Thereafter, data is presented in a serial form from a plurality of serial registers to the output buffer.

Semiconductor memory device equipped with serial data reading circuit

A semiconductor memory device is disclosed, having a plurality of memory cells, from which cell data is read out, based on at least one control signal provided to the memory device. The memory device includes a transfer gate which receives read data from one of the memory cells, a latch circuit which latches the read data sent from the transfer gate, and an output buffer which outputs data produced in accordance with the latched read data. The memory device further includes a transfer gate controller, which produces a latch control signal based on the control signal and supplies the latch control signal to the transfer gate to control an ON/OFF action of the transfer gate. A delay circuit, incorporated in the gate controller, controls level-switching timing for the latch control signal such that after switching the level of the control signal, the transfer gate is turned off with a predetermined delay.

Growing community of inventors

Kasugai, Japan

Yoshiyuki Ishida