Sony Corporation

V Technology Co., Ltd.

Yoshiyuki Enomoto

Ryuichi Kanamura

Tetsuya Komoguchi

Yoshiyuki Tanaka

Hideshi Abe

Kensaku Maeda

Masaki Saito

Kenichi Aoyagi

Toshihiko Hayashi

Hiroyuki Kawashima

Hiroaki Ammo

Kyoko Izuha

Kiyotaka Tabuchi

Keishi Inoue

Masaki Okamoto

Kazunori Nagahata

Yoichi Otsuka

Shingo Takahashi

Hiroshi Sata

Tadayuki Kimura

Iwao Sugiura

A projection exposure apparatus includes a mask mark illumination light source irradiating a mask mark with exposure light itself or a first alignment light having substantially the same wavelength as the exposure light, and an alignment unit having a work mark illumination light source irradiating a work mark with second alignment light having a wavelength different from the wavelength of the exposure light, an imaging device, and an imaging optical system. The imaging optical system includes a first dichroic prism for synthesizing the first alignment light and the light from the work mark and emitting the synthesized light toward the imaging device, and an optical path length changing optical system for splitting and merging the first alignment light, in which the optical positional relationships of the work mark and the image of the mask mark with respect to the imaging device are equivalent.

Projection exposure device and projection exposure method

Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.

Designing method of capacitive element in multilayer wirings for integrated circuit devices based on statistical process

A solid-state imaging device has: an imaging region in which a plurality of pixels each having a photoelectric conversion element are arranged, and a color filter. The color filter includes: filter components of a first color (G), filter components of a second color (R) formed by self-alignment and each being surrounded by the filter components of the first color (G), and filter components of a third color (B) formed by self-alignment and each being surrounded by the filter components of the first color (G).

Solid-state imaging device, manufacturing method thereof, and electronic device

A solid-state imaging device having a plurality of light-receiving sections which are disposed in a substrate and which generate charge in response to incident light, a planarizing layer which covers predetermined elements disposed on the substrate to perform planarization, a plurality of signal lines disposed above the planarizing layer and a waveguide which guides incident light to each of the light-receiving sections, the waveguide passing through the space between the plurality of signal lines.

Solid-state imaging device and method for fabricating the same related application data

In order to form an aluminum system wiring that does not peel off on an insulating film containing fluorine and to improve the reliability thereof, a semiconductor device according to the present invention includes an insulating film () containing fluorine formed on a substrate (), a titanium aluminum alloy film () formed on the insulating film () containing fluorine, and a metallic film () comprising aluminum or an aluminum alloy formed on the titanium aluminum alloy film ().

Semiconductor device and method of manufacture thereof

By improving the embedding property of a light-transmissive material constituting a waveguide, light collection efficiency is improved, and reliability of a solid-state imaging device is ensured. In a solid-state imaging device including a light-receiving section () which performs photoelectric conversion in response to receipt of light and a waveguide () composed of a light-transmissive material formed in an insulating filmwhich covers a substrate provided with the light-receiving section (), in which the waveguide () guides incident light from outside to the light-receiving section (), the waveguide () is provided with a forward tapered portion in which the size of the planar shape viewed from the direction of incident light decreases from the light incident side surface toward the light-receiving section.

Solid-state imaging device and production method therefor

The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film. The second-mask forming layer is etched through the fourth mask to thereby form a second mask having the interconnect trench pattern, and the first insulating film that remains under the bottoms of the via holes is removed. Subsequently, the second insulating film is etched through the second mask to thereby form an interconnect trench, and then the second mask is removed.

Method of manufacturing semiconductor device and semiconductor device

A semiconductor device and a method of manufacturing the device includes a first buried wiring, a second buried wiring formed as a layer different from the first buried wiring, a contact hole, which is formed between the first buried wiring and the second buried wiring and is filled with a wiring material for electrically connecting the first buried wiring and the second buried wiring therethrough, and a dummy hole, which has a hole diameter different from the contact hole, is so formed in vicinity of the contact hole as to connect the first buried wiring, and is filled with a wiring material therein.

Semiconductor device and method of manufacturing the same

A solid-state image pickup deviceis constructed in which a waveguideis formed in an insulating layer on a light-receiving sensor portiona side wallof the waveguideis covered with a reflective filmmade of an Al film deposited by a CVD method, an underlayer filmis formed between the reflective filmand the side wallof the waveguideand the underlayer filmis made of a VIb-group element. It is possible to obtain a solid-state image pickup device including a waveguide in which hydrogen supplied to the light-receiving sensor portioncan be restrained from being absorbed by the underlayer filmand which has the reflective filmof high reflectivity with satisfactory surface condition, satisfactory coverage and excellent adhesion.

Solid-state image pickup device with non-hydrogen-absorbing waveguide

Disclosed is a semiconductor device which has a wiring structure including a small-width wiring connected to a large-width wiring through a connection hole or holes formed in an inter-layer insulation film and in which reliability of wiring can be enhanced by regulating the number of the connection hole or holes and the location(s) of the connection hole or hole. The semiconductor device includes first wirings (), (), an inter-layer insulation film (not shown) covering the first wirings (), (), second wirings (), () connected to the first wirings (), () through the connection holes formed in the inter-layer insulation film, the first wirings (), () being formed to be larger in width than the second wirings (), (), wherein a plurality of the connection holes (), () and connection holes () to () are provided, and the plurality of the connection holes (), (), () to () are disposed at intervals between the connection holes (), () and between the connection holes () to () within the range of from 1 to 18 times the connection hole diameter.

Semiconductor device and method of manufacturing same

An improved method for producing a semiconductor device with a fluorine-doped silicon oxide interlayer insulating film. In one embodiment, the fluorine-doped silicon oxide layer (FSG layer) is formed in a process chamber. Thereafter, a silicon oxide layer is formed in the same process chamber over the FSG layer at a higher temperature than the FSG layer formation temperature. In another embodiment, after the FSG layer is formed, a surface layer of the FSG layer is selectively sputtered away before the silicon oxide layer is formed.

Production method of semiconductor device

To provide a method for producing the semiconductor device in which contactability between a dielectric layer and a contact layer is not reduced during the formation of a metal plug, the method comprises forming a semiconductor device including a base; forming a lower conductive layer on the base; forming a dielectric layer formed on the lower conductive layer; forming an opening in the dielectric layer for electrically connecting the lower conductive layer with an upper conductive layer to be formed on the dielectric layer; forming a first contact layer formed on at least a bottom surface of the via hole and made of a single TiON layer, any portions of said first contact layer formed on the dielectric layer being removed; forming a second contact layer over an entire exposed surface of the first contact layer, depositing tungsten on the second contact layer by a chemical vapor deposition method; and removing portions of the second contact layer formed on the dielectric layer while leaving a tungsten plug and the first and second contact layers within the opening to form a via hole contact.

Growing community of inventors

Kanagawa, Japan

Yoshiyuki Enomoto