Fujitsu Corporation

Yoshiyasu Doi

Hirotaka Tamura

Takashi Shiraishi

Yuji Takahashi

Hiroyuki Fukuda

Hisakatsu Yamaguchi

Takuji Yamamoto

Hiroshi Endo

Shigeto Suzuki

Yasufumi Sakai

Takushi Hashida

Michiko Shiraga

An apparatus calculates, based on attribute information of a new job and jobs that have been executed, a first similarity level of the attribute information between the new job and the jobs by using a calculation expression, identifies a job whose attribute information is most similar to that of the new job as a first candidate job, and estimates power consumption to be consumed by the new job at power consumption of the first candidate job. The apparatus calculates, for at least one of the jobs, a second similarity level of power consumption between the at least one of the jobs and the new job, identifies a job whose power consumption is most similar to that of the new job as a second candidate job, and adjusts the calculation expression to increase the first similarity level to be calculated between the new job and the second candidate job.

Estimation of power consumption for a job based on adjusted calculation of similarities between jobs

A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.

Bias circuit with a replica circuit for an amplifier circuit and a generation circuit supplying bias voltage to the replica and amplifier circuits and optical receiver

A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.

Reception circuit and semiconductor integrated circuit device

A communication system includes: a plurality of lanes; a plurality of transmission circuits respectively outputting data to the lanes in accordance with a transmission clock; and a plurality of reception circuits respectively receiving data from the lanes, each reception circuit includes: a clock data recovery circuit extracting own clock information from received data: a clock information switch circuit selecting either one of the own clock information of the reception circuit or another own clock information of an another reception circuit; a phase shifter generating a phase adjusted clock from a common reception clock source in accordance with clock information selected by the clock information switch circuit; and an input circuit taking in transmitted data in accordance with the adjusted clock, and the clock information switch circuit selects the own clock information in a normal operation and selects the another own clock information in an eye-opening measurement operation.

Communication system, receiver, and eye-opening measuring method

A receiving circuit includes: an interpolation circuit that generates, by using an interpolation coefficient, output data including a data point and a boundary point from pieces of input data that are input in chronological order; a detection circuit that outputs a detection signal when the detection circuit detects a phase of the output data by using the boundary point of the output data; a low pass filter that filters the detection signal and generates the interpolation coefficient; and a modulation circuit that modulates, by using a modulation signal having a frequency different from a cutoff frequency of the low pass filter, the interpolation coefficient generated by the low pass filter, and outputs the modulated interpolation coefficient to the interpolation circuit.

Receiving circuit and communication circuit

An interpolation circuit includes: a first node to receive a first current; a second node to receive a second current; a third node to receive a third current; a first capacitor circuit including: first capacitors; a first switch to couple one end of each of first capacitors to one of first and second nodes; and a first output coupled to the other end of each of first capacitors; a second capacitor circuit including: second capacitors; a second switch to couple one end of each of second capacitors to one of second and third nodes; and a second output node coupled to the other end of each of second capacitors; and a third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch to couple the other end of the third capacitor to one of first and second output nodes.

Interpolation circuit and reception system

An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Interpolation circuit and receiving circuit

A receiver circuit includes: a first sampling circuit to sample input data in synchronization with a first edge of a sampling clock signal; a second sampling circuit to sample the input data in synchronization with a second edge of the sampling clock signal; a duty-cycle-distortion detection circuit to detect a duty-cycle-distortion amount indicating an error in a duty ratio of the sampling clock signal based on first data which is sampled by the first sampling circuit and second data which is sampled by the second sampling circuit; a correction circuit to correct the first data or the second data to generate first corrected data or second corrected data, respectively, based on the duty-cycle-distortion amount; and a clock data recovery circuit to select data out of the first corrected data and the second data and to recover the selected data.

Receiver circuit

A receiving circuit includes a clock generation circuit that generates a clock signal, an integration filter that stores a signal potential of an input signal and generates a first storage potential in a period in which the clock signal indicates one logic, a first analog-to-digital circuit that converts the first storage potential into a first digital value, and a data determination circuit that determines a logic of the input signal on a basis of the first digital value.

Data receiving circuit determining logic of input signal based on digital value

A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.

Parallel-serial conversion circuit and data receiving system

A data transmitting circuit includes a reflection suppressive component generating circuit for generating a reflection suppressive component for suppressing the reflection caused by the discontinuity in the characteristic impedance on a transmission line, and a data output circuit for amplifying the reflection suppressive component and the data to be currently transmitted to a receiving side and outputting them to the transmission line.

Data transmitting circuit and transmitting method

A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.

Data receiving circuit that can correctly receive data, even when high-speed data transmission is performed, using small amplitude clock

A charge pump circuit comprises two MOS transistors serially connected between a power supply voltage VDD and ground, a switch SW, four switches SWthrough SW, four capacitors Cthrough C, and four switches SWthrough SW. If a control voltage Vcntl is to be varied, a specific switch SW of the switches SWthrough SWis turned on such that a specific capacitor is charged to the power supply voltage VDD. Then, a specific switch SW of the switches SWthrough SWis turned on to transfer the electric charge stored in the capacitor to the capacitor of a low-pass filter and thereby the control voltage is controlled at a desired value.

PLL circuit and semiconductor integrated device

An input integrating circuit and a differential amplifier circuit are provided in a receiver circuit which samples a pair of differential input signals, detects the levels of said pair of input signals, and latches the detected levels. The above-mentioned input integrating circuit further includes: a pair of input transistors receiving the pair of input signals at respective gates thereof; a switch transistor becoming conducting in response to a sampling clock in a sampling period so as to supply a discharge current to a common source terminal of the pair of input transistors; and a precharge circuit precharging drain terminals of the pair of input transistors in a precharge period. The input integrating circuit discharges the capacitor of the drain terminals by the discharge current in the sampling period succeeding the precharge period. The differential amplifier circuit amplifies the drain terminals of the input integrating circuit.

High-speed input signal receiver circuit

A receiver for bidirectional signal transmission, where signals are sent and received in both directions over a signal transmission line, has a signal line, a first hold capacitor, a signal line voltage buffer circuit, a hybrid circuit, and a decision circuit. The signal line is connected to the signal transmission line, the first hold capacitor is used to hold a signal, and the signal line voltage buffer circuit is used to buffer a voltage of the signal line. Further, the hybrid circuit is used to output a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit, and the decision circuit is used to make a decision on the logic value of the received signal separated and output by the hybrid circuit.

Receiver, hybrid circuit, driver circuit, and signal transmission system for bidirectional signal transmission for carrying out such signal transmission in both directions simultaneously

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Kawasaki, Japan

Yoshiyasu Doi