Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Yoshiya Moriyama

Hiromasa Fujimoto

Nobuyoshi Takahashi

Keita Takahashi

Susumu Akamatsu

Kosaku Saeki

Hiroshi Ohkawa

Koji Yoshida

Yuji Harada

Satoru Ito

Takahiko Hashidzume

Satoru Itou

Kiyoshi Kurihara

A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.

Solid-state imaging device and method of manufacturing the same

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes first offset sidewalls formed on side surfaces in a gate width direction of a first gate electrode, second offset sidewalls formed on side surfaces in a gate length direction and the side surfaces of the gate width direction of the first gate electrode with the first offset sidewalls being interposed between the second offset sidewalls and the first gate electrode, and first extension regions. The second MIS transistor includes third offset sidewalls formed on side surfaces in a gate length direction and a gate width direction of a second gate electrode, fourth offset sidewalls formed on the side surfaces in the gate length and width directions of the second gate electrode with the third offset sidewalls being interposed between the fourth offset sidewalls and the second gate electrode, and second extension regions.

Semiconductor device

A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor.

A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount dfrom the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1&#x3c;0.5s.

A semiconductor device includes a MIS transistor. The MIS transistor includes an active region surrounded by an isolation region in a semiconductor substrate, a gate insulating film formed on the active region and the isolation region, and having a high dielectric constant film, and a gate electrode formed on the gate insulating film. A nitrided region is formed in at least part of a portion of the gate insulating film that is located on the isolation region. A concentration of nitrogen contained in the nitrided region is nx, and a concentration of nitrogen contained in a portion of the gate insulating film that is located on the active region is n, wherein a relationship of nx&#x3e;n is satisfied.

A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned in the same row; and a protective diode region formed in the semiconductor region to be separated from the memory cell array region. In the protective diode region, a protective diode element is constructed by making a junction between a first diffusion layer of a second conductivity type formed in the upper portion of the semiconductor region and the semiconductor region. Each of the word lines extends to the protective diode region and is brought into direct connection to the first diffusion layer of the second conductivity type, thereby making electrical connection to the protective diode element.

Semiconductor memory device and method for manufacturing the same

A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.

Growing community of inventors

Osaka, Japan

Yoshiya Moriyama