Japan Aerospace Exploration Agency

High-reliability Engineering & Components Corporation

Yoshiya Iide

Satoshi Kuboyama

Akiko Makihara

Hiroyuki Shindou

Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (PPNN). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (I).

Growing community of inventors

Tsukuba, Japan

Yoshiya Iide