Renesas Electronics Corporation

Yoshitsugu Kawashima

Shinichi Uchida

Hiroshi Ise

Takeshi Watanabe

Hiroyasu Kitajima

Junya Ishii

Tatsuki Kojima

Hirofumi Saitou

A semiconductor device includes an interlayer insulating layer disposed over a semiconductor substrate, and including a plurality of wiring layers; a seal ring disposed in the interlayer insulating layer, and surrounding a circuit region of the semiconductor substrate; a crack lead ring disposed in the interlayer insulating layer, and surrounding the seal ring; and a protective film disposed over the interlayer insulating layer, and covering the crack lead ring and the seal ring. The crack lead ring includes an uppermost wiring layer in an uppermost layer of a plurality of wiring layers. When the crack lead ring has a wiring in an underlayer below the uppermost layer, the uppermost layer wiring extends towards the outside of the device, relative to the wiring in the underlayer. The protective film has an end overlapped with an end of the uppermost layer wiring to form a step over the interlayer insulating layer.

Semiconductor device having crack-resisting ring structure and manufacturing method thereof

A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

Method for manufacturing semiconductor device, semiconductor chip, and semiconductor wafer

In a wafer, a first chip region and a second chip region are separated from each other by a dicing region. The dicing region includes: a first center region; a first intermediate region located on the first chip region's side of the first center region; a second intermediate region located on the second chip region's side of the first center region; a first outer region located on the first chip region's side of the first intermediate region; and a second outer region located on the second chip region's side of the second intermediate region. Surfaces of the first and second intermediate regions are respectively covered by bank-shaped resin films extending in a longitudinal direction of the dicing region. Respective surfaces of the first center region, the first outer region and the second outer region are not covered by resin films.

Wafer and method of manufacturing semiconductor device

A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.

A method for manufacturing a semiconductor device includes forming a semiconductor wafer including a plurality of interconnect layers, the semiconductor wafer including: a plurality of chip-composing portions; a dicing region separating the chip-composing portions from each other; and a plurality of inter-chip interconnects electrically connecting adjacent ones of the chip-composing portions and formed in one of the interconnect layers and in the dicing region; a dummy metal pattern comprising a plurality of dummy metals, the dummy metal pattern being formed in at least one of the interconnect layers over or below the inter-chip interconnects only in an area corresponded to a region where the inter-chip interconnects are arranged and corresponded to a region therearound; and forming semiconductor chips by dicing the dicing region so as to divide the chip-composing portions.

Method for manufacturing a semiconductor device, semiconductor chip and semiconductor wafer

An improved yield of chips is realized by reducing the width of dicing streets on the front surface side of a semiconductor wafer. A method for semiconductor chip, divided a semiconductor waferhaving a plurality of circuit patterns formed on one surfaceinto pieces, comprising, forming a groove in a boundary region between the circuit patterns from the other surfaceof the semiconductor waferby using a blade, forming a modified layerin the boundary region between the circuit patterns by irradiation with laser light L from the one surfaceor the other surface 19 of the semiconductor wafer, and dividing the semiconductor wafer into pieces by breaking the modified layer. The modified layeris formed between a bottom surfaceof a groove portionand the one surfaceof the semiconductor wafer, and a forming width WM of the modified layeris smaller than the width of the groove portion

Growing community of inventors

Kanagawa, Japan

Yoshitsugu Kawashima