Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Subaru Corporation

Ricoh Company, Ltd.

Yoshitsugu Inoue

Hiroyuki Kawai

Robert Streitenberger

Junko Kobara

Hiroyasu Negishi

Keijiro Yoshimatsu

Masahiro Yamada

Yoshiyuki Kato

Mitsuo Aoki

Shinichi Uramoto

Masatoshi Kameyama

Hiroyuki Morinaka

Hiroyuki Akiyama

Shinya Sagawa

Akihito Katsume

Satoki Ishii

Takahiro Kawashiri

Shotaro Suzuki

Go Yanagisawa

Tong Wang

Kyousuke Kuroda

Toru Noro

Tomoyuki Yamamuro

Hisashi Nakamura

Hiroshi Segawa

Kazuya Ishihara

Takeo Nakabayashi

Shinichi Nakagawa

Yoshinobu Yamazaki

Chikako Ikenaga

Harufusa Kondo

Masami Oguri

Akira Torii

Nelson Chan

Atsushi Kurimoto

An information processing apparatus includes one or more processors and one or more storage media storing a program. The program includes one or more instructions that cause the one or more processors to execute acquiring information on a current location of a vehicle and a destination of the vehicle; acquiring one or more scheduled travel routes for reaching the destination from the current location; acquiring current weather information; predicting a standstill section in which a standstill situation is likely to occur on the one or more scheduled travel routes; predicting a standstill time during which a standstill situation occurs in the predicted standstill section; calculating heating power consumption due to use of heating over the predicted standstill time; performing a determination as to whether to additionally charge a traveling battery of the vehicle in accordance with the heating power consumption; and presenting information corresponding to a result of the determination.

Information processing apparatus

A drive motor control system performs control of a drive motor of a vehicle that includes the drive motor and a battery. The drive motor control system includes a control processor that controls an electric current supply from the battery to the drive motor and includes an operational state determiner that determines whether a condition that the vehicle is being stopped, a condition that a parking brake is being released, and a condition that a parking range is being selected are satisfied. When the operational state determiner determines that all the conditions are satisfied upon a reception of a trigger signal instructing a start of the control of the drive motor, the control processor performs control of an inverter such that the electric current supply is performed to cause the drive motor to repeat small reverse rotations and thereby induce small movements of the vehicle in front and rear directions.

Drive motor control system and snow removal system for vehicle

A vehicle driving device mounted on a hybrid vehicle includes an engine coupled to wheels of the vehicle via a power transmission path, a transmission mechanism disposed on the power transmission path, a motor generator, a first power transmission mechanism, and a second power transmission mechanism. The motor generator is disposed on a path coupling the engine and transmission mechanism, the first power transmission mechanism is disposed on a path coupling the engine and motor generator, the second power transmission mechanism is disposed on a path coupling the motor generator and transmission mechanism. These paths are included in the power transmission path. The first power transmission mechanism includes a large-diameter rotator and a small-diameter rotator coupled to the engine and the motor generator respectively. The second power transmission mechanism includes a small-diameter rotator and a large-diameter rotator coupled to the motor generator and the transmission mechanism respectively.

Vehicle driving device

A vehicle control apparatus, configured to control a vehicle, includes an engine that is configured to drive wheels via a power transmission device. The vehicle control apparatus includes a towing state detector and an engine controller. The towing state detector is configured to detect whether the vehicle is in a towing state. The engine controller is configured to stop the engine in a case where a predetermined engine stopping condition is satisfied during traveling of the vehicle. The engine controller is configured to vary, in a case where the towing state detector detects that the vehicle is in the towing state, the predetermined engine stopping condition to reduce an operational range in which the engine is to be stopped compared with an operational range in a case where the towing state detector does not detect that the vehicle is in the towing state.

Vehicle control apparatus

A vehicle includes a transmission shiftable by hydraulic pressure, a main oil passage that delivers operating oil, a first oil passage that delivers the operating oil from the main oil passage to the transmission, a first valve that opens/closes the first oil passage, a controller that controls the first valve, a second oil passage that delivers the operating oil from the main oil passage to the transmission, and a manually drivable second valve that opens/closes a section of the first oil passage that is closer to the main oil passage than the first valve and the second oil passage. The second valve is switchable between the automatic control state in which the first oil passage is opened and the second oil passage is closed and the manual control state in which the first oil passage is closed and the second oil passage is opened.

Vehicle

The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance with a predetermined algorithm, such that each of the devices on the secondary ports receives and responds to exactly a single access; and terminating configuration cycles after distributing the plurality of configuration accesses.

Method and apparatus for routing configuration accesses from a primary port to a plurality of secondary ports

An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the host CPU can directly write the vertex data, which does not require a geometry process, to a rendering process apparatus and a processing speed of an overall graphics system can be thereby improved.

Rendering process apparatus capable of improving processing speed of overall graphic system

A clock control unit () detects completion of data processing based on a busy signal BSYoutput by a geometry processing unit () and a busy signal BSYoutput by a rendering processing unit (). The clock control unit () controls supply of a clock signal CLKto the geometry processing unit () and supply of a clock signal CLKto the rendering processing unit () so as to cause the geometry processing unit () and the rendering processing unit () to alternately operate.

3-dimensional graphic plotting apparatus

A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q to q ) include carry output prediction circuits ( to ), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i&minus;1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i&plus;1), respectively.

Square root extraction circuit and floating-point square root extraction device

A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include all arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.

Graphic processor having multiple geometric operation units and method of processing data thereby

A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.

Logarithmic arithmetic unit avoiding division as far as predetermined arithmetic precision is guaranteed

An FIFO data transfer control device includes an instruction analyzing portion for analyzing an instruction for data transfer to an FIFO storage device including a plurality of banks, and calculating an amount of data to be transferred; a data count portion for calculating, from the data amount calculated by the instruction analyzing portion, an amount of the data written in the bank being in an outputting state, and issuing a determination flag indicating whether the free space of the bank being in the outputting state satisfies predetermined conditions or not; and a full check portion for inhibiting processing of a next instruction until the determination flag sent from the data count portion or the full flag issued from the FIFO storage device is reset.

First-in first-out data transfer control device having a plurality of banks

A bridge includes a first port connected to a Primary bus, and second ports respectively connected to second buses. The first port includes a PCI master, a PCI slave and an AGP master. Each of the second ports includes a PCI master, a PCI target and an AGP Target. The bridge further includes a plurality of first-in-first-out memories forming asynchronous data paths between the first port and the second ports and arbitrators for arbitrating a contention between the transactions on the data paths formed by the first-in-first-out memories based on the protocols related to the transactions.

Bridge device for connecting multiple devices to one slot

The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.

Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel

In a floating point adder adding received two floating point data together and subtracting one such data from the other, before their exponent parts are matched in digit by a digit match unit the two data have their exponent parts compared and also their fraction parts compared, and a result of each comparison and a sign of each data are used to code a relationship in magnitude between data corresponding to a clipping coordinate and the other data fed. A clip code generated depending on the previously obtained comparison results from exponent part and fraction part compare units, rather than depending on a zero flag according to a result of an addition or a subtraction and a sign of the result of the addition or the subtraction, can rapidly be generated without the circuit increased in scale.

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Hyogo, Japan

Yoshitsugu Inoue